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Found 5 results

  1. Hello sir We purchased "Arty-Z7-20" a few weeks ago. We are trying to boot a project using the petalinux. We have followed the manual given in the below links. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug1144-petalinux-tools-reference-guide.pdf https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1157-petalinux-tools-command-line-guide.pdf But the Arty-Z7-20 board didn't get booted via jtag or SD card. We have also followed steps provided on belowed github, but it won't work.. https://github.com/Digilent/Petalinux-Arty-Z7-20 Output while running boot command shown below, '$ petalinux-boot --jtag --prebuilt 3 --hw_server-url TCP:' INFO: Sourcing build tools WARNING: Will not program bitstream on the target. If you want to program bitstream, WARNING: please run petalinux-package --prebuilt to put the bitstream to the prebuilt directory, WARNING: or use --fpga --bitstream option to specify a bitstream. INFO: Append dtb - /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/system.dtb and other options to boot zImage INFO: Launching XSDB for file download and boot. INFO: This may take a few minutes, depending on the size of your image. rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.: Inappropriate ioctl for device INFO: Downloading ELF file: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/zynq_fsbl.elf to the target. INFO: Downloading ELF file: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/u-boot.elf to the target. INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/system.dtb at 0x00100000 INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/uImage at 0x00200000 INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/rootfs.cpio.gz.u-boot at 0x04000000 INFO: Loading image: /home/harshil/FPGA/Project_Petalinux/project_linux/pre-built/linux/images/boot.scr at 0x03000000 INFO: SOC Silicon version is 3.1.
  2. rob2018t

    Arty Z7 and Reset

    Hello fellow Digilent Members, I hope everyone is well. My Skill Level: I'm slowly progressing my knowledge of FPGA and Vivado using the Digilent Arty Z7-20 and Arty S7-50. Essentially quite a beginner and I've created simple RTL designs to flash LEDs, utilised the Microblaze, Zynq and made a AXI-4 IP block. All really exciting stuff IMO...I just need to make something more useful now. My Question: when designing with the Arty S7-50 I'm able to specify the board and then drag across the reset into my top diagram and/or utilise that when auto completing the design. However in the Arty Z7-20 design there is nothing listed like this in the board peripherals tab (is shows the switches, buttons, LEDs etc). Indeed there is nothing in the XDC constraints file either. I do see that my board is a Rev. B and that the board.xml is only for rev A.0 - I cannot find anything newer. Could someone please advise how to add the reset into my design please for the Arty Z7-20 ? I'm on different computers for the Vivado and my email access so sharing of screenshots or listings will be a little slow (not impossible though if it helps someone determine any issues). many thanks for any consideration :-)
  3. Hi, Background: I am sending 3 channels of digitized 12-bit (soon to be 16-bit) data over "long" distances (thus I will be sending the data using LVDS). I will also be sending a 40 Mhz clock signal over LVDS so in total, that will be 3 data channels + 1 clock (= 4 channels x 2 wires/channel = 8 wires). The data rate is 600-720 Mbps per channel for 12-bit and up to 960Mbps per channel for 16-bit for the data lines. Question(s): I would like to use the HDMI connector on the Z7-20 board to get the data in. Is that possible? If so, I would appreciate any information as to how to go about doing this. HDMI has a number of LVDS lines (actually TDMS) and I would like to take advantage of the built in hardware to include deserialization of the data and memory storage. TDMS uses 9/10 bit data but I will use 12 bit to 16 bits. Is the data size fixed in hardware or would I be able to configure that? I'm new to FPGAs but can the data get pipelined directly into memory? If so, is there a way to set the bit endianness as it gets stored into memory? If the above is solvable, I would like to know if I can use both HDMI connectors to do this (I will actually have 2 sensors), both the HDMI in and HDMI out. In theory I just need the data lines and access to memory so I wouldn't think that this would be a problem on the HDMI out as well, but I don't know...which is why I'm asking. If the above isn't possible, are there any other options? I can make an adapter board and deserialize the data to CMOS/TTL digital IO and use the PMOD or shield connectors to send the data to the FPGA but this would be 12 bits/channel x 3 channels = 36 bits at 40 Mhz, (48 bits for 16 bit data). That doesn't leave me very many (or any) lines for output but if that is my only option, is 40 Mhz considered high speed? Thanks in advance.
  4. Hi, I asked this on the Xilinx forums too, but so far no one has answered. Maybe someone here can help. I bought a arty-7z-20, so I could learn more about FPGA's. I downloaded Vitis+Vivado 2020.1, and followed some tutorials (for example this one https://nuclearrambo.com/wordpress/programming-the-zynq-7000-with-vivado-2019-2-and-vitis/) but they all have the same basic steps. The Vivado side is clear, I can generate a bitstream and export it to a board. I can also create the HDL wrapper, and export the xsa file. But now when I open Vitis, I should create a new platform project, or create a new application project depending on the tutorial I'm following. But in both I import the xsa file which was created using Vivado. Now when I try to create the project and 'create a new platform from hardware', then select the generated xsa file, it always take about 10-15 minutes saying 'reading hardware specification', then fails saying I need to select the processor type. But there are no processors available. How can I add processors to the list? Do I need to download more files somewhere? I've tried this on Win10, and also Linux. Both the same result. So it's probably just something I've done, but I don't know. I'm a bit lost now. Any hints or tips? Thanks!
  5. Hi, I'm trying to boot petalinux from TFTP server and NFS root based on Arty Z7-20 Petalinux BSP Project (https://github.com/Digilent/Petalinux-Arty-Z7-20) Unfortunately, TFTP boot method is not included in the Project's README.md file. I found several useful infromation and tried them to my Arty-z7-20 board. [1] TFTP Boot and NFS Root Filesystems : https://elinux.org/TFTP_Boot_and_NFS_Root_Filesystems [2] Petalinux with Root NFS and Kernel on TFTP sever : https://www.youtube.com/watch?v=DHmcjkDDAlM [3] running netboot with u-boot-xlnx : https://forums.xilinx.com/t5/Embedded-Linux/running-netboot-with-u-boot-xlnx/td-p/760236 It was passed to access TFTP server on HOST PC (Ubuntu 18.04). However, I failed to access NFS Root Filesystems on Host PC. These were Host-PC settings netplan Static IP : gateway4 : /etc/exports /srv/nfsroot, sync, no_root_squash, no_subtree_check) TFTP server directory : /var/lib/tftpboot files : BOOT.BIN, image.ub, zynq_fsbl.elf etc... settings (/etc/default/tftpd-hpa) TFTP_USERNAME="tftp" TFTP_DIRECTORY="/var/lib/tftpboot" TFTP_ADDRESS=":69" TFTP_OPTIONS="--secure" NFS Root directory : /srv/nfsroot files : root files extracted from rootfs.tar.gz And, these were Petalinux settings Ethernet Settings Static IP address : Static IP netmask : Static IP gateway : Image Packaing Configuration Location of NFS root directory : /srv/nfsroot NFS Server IP address : tftpboot directory : /var/lib/tftpboot I started TFTP and NFS servers on Host-PC $ sudo service tftpd-hpa restart $ sudo service nfs-kernel-server restart After copying BOOT.BIN file to SD-card and inserting it to Arty-z7-20 board, I powered up the board and checked the status of server on Host-PC Zynq> ping Using ethernet@e000b000 device host is alive Downloading "image.ub" file from TFTP sever is successful. Zynq> tftpboot image.ub Using ethernet@000b000 device TFTP from server; out IP address is Filename 'image.ub'. Load address: 0x10000000 Loading: ########################################## ########################################## 9 MiB/s done Bytes transferred = 3779188 (39aa74 hex) I started netboot and got kernel panic error Zynq> run netboot ... ALSA device list: No soundcards found. VFS: Cannot open root device "(null)" or unknown-block(0, 0): error -6 Please append a correct "root=" boot options; here are the available partitions: ... ---[end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)... This is expected correct message from ref. [2] Could you help me find the problems? Thank you!
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