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Found 15 results

  1. I tried to use Eclypse Z7 and ADC 1410 to collect the Sin wave signal which is between -5V to 5V, but I found something strange. The channel 1 just gets -4.6V to 5V and the channel 2 just gets -5V to 4.6V. They all cannot get the whole signal from -5V to 5V. Is that the problem about the hardware or the programming? Thanks for any suggestion.
  2. Hello everyone, I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits. I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)? I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs. Thank you! Regards H
  3. Div_01

    Nexys2 FPGA board

    Hi, I am a newbie to FPGA. Does the Xilinx Spartan 3E Nexys2 FPGA board contain internal ADC and DAC? If yes, which are the ports for it? Thanks & Regards, Divya
  4. Hi Digilent Masters, I'm starting to work on a mini project which reading back PmodAD2 VinX data from Arria 10 FPGA dev kit through I2C interface. I'm using Quartus to develop the code, and enabled weak pull up resistor on both SCL & SDA in Quartus The Vcc is connected with 5V and Vin1 - Vin4 are connected with inputs which have max 1.8V. When I measure my SCL with DMM, it shows only 1.4V when HIGH and drops to 0.3 when SCL goes LOW. From the PmodAD2 schematics, it tells me this is definitely not meeting the requirements. What did I do wrong? FYI, I'm new to FPGA design Would be appreciated if anyone can offer their insights on this issue. Regards, Lucas Kang
  5. Hi, I want to read analog data from ad1 pmod. For Vivado part, I use digilent pmod ips to connet fpga. For SDK part, I use AD1.h and AD1.c library in examples. My sensor sends to me analog values between 0-3.3V. (This is a heart rate ECG values). During using arduino, all heart beat data can be read. But I use same function for zedboard, Analog values doesnt look like arduino's. How I can configure and fix this problem? As you see ad1-zedboard connection as below.
  6. I'm trying to get the Pmod Color module for the Zynq z7-10 to work but it doesn't appear to be on. I was following along the instructions from these sites: https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start https://projects.digilentinc.com/arthur-brown/displaying-color-readings-with-the-pmod-color-and-python-ebd794 and I have it connect to the device as such on the board's JA port: Following along with the first link, I skipped the steps where a clock and interrupt were added as the data sheet shows that the Pmod Color IP does not require these. I have included my schematic below. I see that the module has an LED pin (LD1) but it doesn't appear to be on when connected to my powered device. In the SDK, I added a debug 'else' statement to the main() portion of the code to see if the Pmod is receiving data. After running the code on the board, the else statement is the only statement being executed. What could be the issue that my module is not turning on? I took a voltmeter reading, and the Vcc and GND pins are getting 3.3V. Following the instructions of the first link, I noticed they never included a constraints file. Could this be the issue? zynq_ps_main_c.c
  7. hello ! i am using pmodAD5 connected with arduino uno . i am looking to use the onboard AD7193 in continuous conversion mode to measure the data , but i am unable to get the correct and desirable conversion results. Can anyone help me with this . i hereby attach the respective code and library i am using for my task. AD7193.h AD7193_Voltage_measure_final.ino AD7193.cpp
  8. Norbert96

    ADC FPGA connection

    Hi! I have been working on a digital filter in LabVIEW for and ADC called AD7402. Can somebody explain the following codesequence? I don't understand what it does. I can find all the code in the datasheet of the ADC in the attachments. WORD_CLK = output word rate */ always @ (negedge word_clk ) begin case ( dec_rate ) 16'd32:begin DATA <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0}; end 16'd64:begin DATA <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2]; end 16'd128:begin DATA <= (diff3[21:5] == 17'h10000) ? 16'hFFFF : diff3[20:5]; end 16'd256:begin DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; end 16'd512:begin DATA <= (diff3[27:11] == 17'h10000) ? 16'hFFFF : diff3[26:11]; end 16'd1024:begin DATA <= (diff3[30:14] == 17'h10000) ? 16'hFFFF : diff3[29:14]; end 16'd2048:begin DATA <= (diff3[33:17] == 17'h10000) ? 16'hFFFF : diff3[32:17]; end 16'd4096:begin DATA <= (diff3[36:20] == 17'h10000) ? 16'hFFFF : diff3[35:20]; end default:begin DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; end endcase end AD7402.pdf
  9. Hi! I want to read the output data of a delta-sigma modulation based ADC (AD7402) using NI LabVIEW FPGA. Can you help me by explaining what the Verilog code in the attached datasheet (page 17) does? AD7402.pdf
  10. Hello, this is my first post in this forum. Im working on a project which I should sample data from ADC (ADS5463), and then fft the sampled data and see the results. The sampling clock is 400MHz and my FPGA working with DRY clock coming from the ADC which is 200MHz (fs/2). Im sampling the data with DDR interface using Lattice IP (GDDRX1_RX.SCLK.Aligned Interface), which sampling 12 bit DDR data into a bus of 24 bit (there the 11:0 bits is positive edge data and 23:12 is the negative edge data). Next Im storing this data into 2 FIFOs, one for the positive edge data and another for the negative edge data. My next step which Im currently working on is to insert this data into the FFT IP module which Lattice provides. (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwiBl_HfzovoAhVKY5oKHfNPBt0QFjABegQIAhAB&url=http%3A%2F%2Fwww.latticesemi.com%2Fview_document%3Fdocument_id%3D28236&usg=AOvVaw3HSzLdNneCLsy5wEoUnUOx) I attached timing digrams (timings.pdf). The FFT IP Im creating is 12bit width input/output so I need to time the input flags in a way that it take first data from the positive edge FIFO and the next data from the negative edge FIFO and processing so on in a stream. Of course Im paying attention to all the flags as the IP telling. I want to ask some guidelines questions about how to do it correctly. 1. Do I need a state machine which indicates when the FIFO is full and only then to read the data into the FFT input? Or I can start writing to the FFT without state machine and just counter register which indicate when is read enable asserted and start reading to the FFT? 2. Do I need to fill the FIFO and then read the data until its empty, or I can write to the FIFO and read from the FIFO to the FFT continuously? 3. Any guideline how to make this task correctly? I never did this before.. From my prepective I would just wait for ready flag from the FFT IP and read_enable from the FIFO and start to provide data to the FFT IP but I told the there is more timing managment to be made. thanks. timings.pdf
  11. Hi, I am trying to characterize an ADC by applying a ramp dc value as an input and receiving the digital values in SPI (three-wire option). The Select and Clock are applied (similar to DigitalOut_SPI.py example). I have implemented the test setup in the Waveforms (Analog Discovery) and it is functional. I can see the Digital Value of the ADC both in Logic Analyser and Protocol (SPI - Spy (Three-wire)) (figs attached). I have automated the full procedure using python except the SPI part. I am interested in the first 16 bits after the Select high. I have gone though the examples of the SDK for the spi (Digital_Spi, Digital_Spi_Spy) but it is not clear due to lack of comments. Can you please provide any suggestion? @attila Regards, Chris
  12. I'm a newbie here and I’m working on a inverter test bench project where I have two three-phase inverters connected through an inductive load. The idea is to emulate in real time the behave of an electrical machine. To be clearer, the first inverter is going to be tested (Device Under Test) and the second one plus the inductive load must behave like an electrical machine. To do so, we are going to use a FPGA board, which must have the following specifications: - Capable to drive both inverters switching at 50kHz (each inverter has 6 MOSFETs switching at this frequency) - 20 digital I/O - 4 ADC with 16 bits (ideally) and 20MHz at least. The ADCs can be integrated or not in the FPGA board - Capable to communicate in real time with Matlab/Simulink - The board will be placed inside the test bench, in a temperature around 50°C We know that we are going to use Vivado to the VHDL coding, but we are not sure about the ADCs, regarding the Eclypse Z7 with the two Zmod ADCs. We want to code the least possible in VHDL (no VHDL coding if possible), so my questions are: 1) Are we going to have to code the ADC data acquisition? 2) Is the VHDL code generation done automatically by Matlab? I do have the toolbox for HDL coding. Our budget is around €1000,00. I would like to know if the board Eclypse Z7 with the two Zmod ADCs is a good choice for the application and if you have another advices it would be highly appreciated. I hope I made myself clear. Thank you!
  13. Hi, i have been analyzing signal response from a DUT (a resonator) using network function in waveforms. For comparison, i ran the same setup and parameters on the actuation signal using a lock-in amplifier (MFLI) separately. Both responses are attached below. So far i have been getting very similiar response (from frequency and phase shift perspective), but with a significantly different amplitude. https://imgur.com/a/xlJ2DWM (for some reason i kept failing to upload directly here ) The parameters of the reference signal were: Ampltude: 3V DC-Offset: 2V Frequency: 203.31 kHz I am quite new to signal processing (especially working with an ADC), so i might miss some details that should have been taken into account. Could someone help me explain, what could possibly influence the amplitude different shown on each response? I appreciate your time and response greatly! Regards, Jody
  14. Hi, apparently it is easy to damage something by playing around with the XADC-port (of a Zybo-Z7 in this case). I want to read the charging curve of a capacitor. How I thought this could be done I simulated in LTSpice: 300mv are much less than the maximum 1V and I added R5 and R3 because there are no preresisitors inside XADC-ports. I guess this way my hardware should survive the first time converting an analog voltage curve into digital value. But I'm, just guessing so the two questions I have about this are 1. Is this safe? 2. Is there a better way to do this? and also 3. How sensible are the XADC-Ports really? How high do currents and/or voltages have to be to cause damages? Are maybe the only important rules to prevent short circuits through XADC-hardware by placing a preresistor and prevent voltages above 3.3V? Thank you! /edit Question #4 Would a combination of resistors (one would be enough I think) and Zener-diodes (breakdown at 1V), as you can see below, securely protect any hardware onboard of any mistakes done outside XADC-Pmod? This is just a result of my tiny little knowledge of analog elecronics. Simulation does agree but that is just simulation. Maybe in reality and for a very short time there still could be constellations causing voltages and/or currents that could damage my board... Or is this schematic below really a secure protection? Depending on how XADC-hardware looks inside, theoretically a short circuit current would cause high voltages which should also be taken by the diodes, ...I guess. So are resistors maybe not even needed and only Zener-diodes would already give a safe protection of hardware damages?
  15. hi all, i want want to measure a voltage with the zybo and display the measured values on a screen via hdmi output. i used the hdmi passthrough projent as a start and got that working fine. know when i added the adc in vivado i get the error that the Vccs on bank 35 are incompatibele because the hdmi used 3.3V and the adc uses 1.8V. but when i look in the schematic under synthesis and look and the i/o ports i see that the hdmi aslo uses 1.8V. so why is it a problem when the adc needs 1.8V but when the hdmi needs 1.8V it works just fine.
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