Jump to content

Search the Community

Showing results for tags '@d@n'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 4 results

  1. I had inserted FFT core in a design after FIFO .at the output i am expecting a frequency bin on certain index but i am not getting the result.FFT core is working on 100mhz clock . Following steps i had implemented . - For FIFO to be work on 100 MHz, I verified this by sending the captured data to MATLAB and analyze DATA over there. So I received data correctly. - I inserted FFT core after ADC_FIFO in the reference design. That FIFO working correctly on 100MHz clock. But I didn’t get the correct DATA from the core. For verifying FFT core settings, I debugged FFT core with a DDS core. I mean generate a signal from DDS core and passed to FFT core, at the output I got correct result. So FFT core is also working fine s_axis_data_tdata[31:0] ( input [ real 16 bit , q 16 bit ] ) s_axis_data_tlast (I provide this signal from a counter which run upto FFT points) s_axis_data_tready [ output] s_axis_data_tvalid [coming from fifo] s_axis_config_tdata [ passed 0] s_axis_config_tready [ output] s_axis_config_tvalid [constant 1] m_axis_status_tready [constant 1] m_axis_data_tready [constant 1]
  2. Hello, I am a student from Korea. I am trying to use a on board mic at nexys 4 ddr product. The final goal is to get noise level (such as 80dB). I have problems about understanding pdm modulation which is at page.24 of below pdf file. First of all, I thought I could get the noise level via couting each pdm signal occurs while a one clock pusle(if clock is 3Mhz timing will be 1/3 ns). But I'm not sure this is true. Even if it is true, I cannot find exact counting time to seek exact noise level. Can you help me with how to use on board mic as noise level? (via pdm modulation) I am using verilog. Hope your reply. Thanks. nexys4ddr_rm.pdf
  3. Dear Sir, I am trying to generate Sinusoidal frequency using DDS Compiler in Vivado Block Designing and want to check its FFT Magnitude. I have few Querries to ask. First thing is that what will be the effect on output magnitude and xk_tuser index of FFT, if we use simple SINE or SINE AND COSINE. As in general we get two peaks for sine wave while for SINE AND COSINE we get single peak with added magnitude (please correct me if I am wrong). Secondly, I am not sure whether my FFT Magnitude Block is right or not (Figure Attached) , I have used two Slices at the output of FFT IP m_axis_data_tdata to separate Real and Imaginary parts, but do we need to specify separte MSBS and LSBS in it or not. Third thing is that, if we select SINE and COSINE option in DDS, then in FFT Magnitude block, how many bits for Tuser index will represent Sine and Cosine Magnitude. As Log base 2 (4096) is 12. Expected Index: 50K/ (100M/4096) = 2.048 : 10 DDS Details: Configuration: Phase Generator and SIN COS LUT, System Clock : 100M System Parameters, Implementation: Fixed, Phase Offset: None, Output Selection: Sine and Cosine Frequency 50KHZ FFT Details: Transform Size: 4096, Target Clock:100M, Radix2 Busrt I/O Architecture Implementation: Fixed Point, Block Floating Point, Covergent Rounding Input Data Width:8 , Phase Factor Width: 8 XK_Index, throttle Scheme: Real Time Your kind Response will be highly appreciated.
  4. Dear Sir, I am trying to implement fir compiler in vivado block design. I have generated two frequencies , 200Khz and 1Mhz using DDS Compiler. I designed a Low Pass Filter Using FDATool in Matlab (figure attached). I am analyzing waveform using ILA but FIR Compiler output is either a straight DC or an irregular signal. I have attached Screenshots of block design, filter design and waveform. Your kind response will be highly appreciated.
×
×
  • Create New...