Hmmm... thanks for the information, you just won me a lunch bet. Perhaps you can answer this question. Why is it that people who have time to engage in unproductive nonsense can't use the time to provide useful help.
Here's a suggestion. Instead of posting snarky remarks, just paste one of your AXI master Verilog source files here with a brief description of how you used it. That can't take up much of your valuable time and could help the average user grasp the topic.
Well, I'll offer one way, which is how I do ZYNQ designs. After creating the board design and generating the output products I tell Vivado to create a wrapper file in the project HDL, typically for me in VHDL. This wrapper then gets instantiated into my own toplevel entity where I can connect to any exposed signals that were made external in the board design. Usually, Vivado attaches IO buffers to these signals but will remove them and spit out warnings that can be ignored. You can look over an example here: https://forum.digilentinc.com/topic/20299-fun-with-phasors/
So, in your schematic above the first thing to do is make your UART signals external...
[edit] I forgot a sentence that I always add: When you have Vivado create your wrapper file make sure to de-select the default option that lets Vivado manage the wrapper code. You want to manage this to avoid unnecessary fights with the tools.
