[Zybo Z7-10 : Accessing the Xilinx FPGA over independent JTAG and not over USB2JTAG bridge]

Problem is now solved.

The FPGA can be detected by the XPC USB II debugger.

I am not using the USB2UART bridge. I just use a separate 5V DC power supply to ensure that the bridge is not activated and the debugger is directly connected to the JTAG signals at J13.

[Zybo Z7-10 : Accessing the Xilinx FPGA over independent JTAG and not over USB2JTAG bridge]

Additionally...

If I change the Jumper at JP5 to set Programming Mode = JTAG (instead of default mode, QSPI Flash), will I be able to see the FPGA as device detected through the JTAG interface (J13) at Vivado Lab?

Is this the way to do it?

 

 

[Would using a USB Hub for UART communication cause any issues?]

It will not be a problem to access ther FPGA over a USB Hub.

Take a look into the Device Driver of your PC, all serial connections to the USB will be separately listed.

[Simulation of the Arty Z7-10 with DDR in VIVADO]

@wayyu,

You can use the DDR3 Control IP core provided by Xilinx.

The Ip is free to use.

Using the GUI of the IP you can select AXI as the user_interface for the Ctrl Core.

There is also the Ctrl IP core documentation, MUST read it. Also there is an example_design in there which you MUST try out before creating your custom design.

[is it okay to connect Zybo z7 PMod ports to digital signals through wires?]

@Michael Bradley

I have not taken a look for a long time into the Zybo Z7 pin mapping file. But I can tell you from memory that the PMOD connections are generally connected to the FPGA GPIO pins, so that you can control them as as you like.

So the answer to your question would be a yes!

[Zybo Z7-10 : Accessing the Xilinx FPGA over independent JTAG and not over USB2JTAG bridge]

Board: Zybo Z7-10

Software: Vivado Lab Edition 2020.2

Debugger: Xilinx Platform Cable USB II

When my Zybo Z7-10 board is connected to the PC using the USB cable, the Software  can detect both the PL and PS. All good here!

It is my desire, not to use the USB2JTAG bridge to access the FPGA over JTAG. Instead, I want to use the J13 header (I have soldered the pins in there for connection) for JTAG connection to access the FPGA. The Xilinx Platform Cable USB II has the JTAG cables at one end and I want to plug these into the J13 to have JTAG access. At the end Software needs to identify the FPGA over this direct JTAG connection.

Is it possible? How can I do it? Is there some jumper settings I must change to facilitate this?

Note that I am still using the USB to power the board, so the USB2JTAG is always remaining activated by default. Should I need to change to a 5V DC adapter to power the board when I want to the JTAG over J13?

I have also referred here -  https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual  but did not find any guidance to activate the JTAG over J13 header.

Please advise.

 

[Reading and witing the PL GPIOs using Zynq]

The problem is solved. I used the XGpio_Discrete*() and it worked.

[Zybo Z7 Mobile Phone Control]

I don't know the communication b/w the Pmod ESP32 and the smartphone.

But driving the Pmod from Zybo z720 should be straightforward. You have to implement the SPI master core (you have Xilinx IP cores free to use) on the FPGA side which should be able to read/write to the SPA slave, i.e Pmod ESP32.

[Signal Generation - DDS Compiler, CORDIC, PL, PS - Comparison]

You are not specific regarding the type of "implementation " you mean here - Make own implementation in Micorcontroller Part of SoC; Make own implementation in PL Part or FPGA

1. Signal gen can also be done using look-up tables. Depending on the nature of signal to be generated, the "look-up" table method is supposed to be efficient. The savings in processing time can be significant, because retrieving a value from memory (where loop-up table values are stored) is often faster than carrying out an "expensive" computation or input/output operation.

2. That is your homework, search out and compare!

[Reading and witing the PL GPIOs using Zynq]

Hello,

I have a Z7-10 board. I am writing software for the Zynq, which will access 8 GPIO pins via the PL (using the AXI GPIO IP). These will be 4 each on-board LEDs LD0-LD3 (to be configured as output) and DIP switches SW0-SW3(to be configured as input). The BD is shown below. The offset and high address are shown below in the SS.

My target is to read the status of the 4x slide switches and write those values back to the LEDs in order.

So to achieve that, after initializing the GPIO, I have also set the direction of the bits as shown in the following 2 lines.

Status = XGpio_CfgInitialize(&my_Gpio, GPIO_Config, GPIO_Config -> BaseAddress);

XGpio_SetDataDirection(&my_Gpio, 1, 15); // Only the 4 LSB bits are inputs(4x slide switches), so 1's

 

Now all I have to do is to read the switch status and write them back to the LEDs inside a while loop. However I am not sure how to use the XGpio_ReadReg() or XGpio_WriteReg().

SDK tells me the to use XGpio_*Reg(BaseAddress, RegOffset). But what would be my BaseAddress, RegOffset?

Will it be as shown in the Address Editor, i.e. BaseAddress = 0x4120_0000 and RegOffset = 0x00000000?