[Can I use Pmod CAN V with AMD KR260 Dev kit with Pmod1 in a board]

@rachot

Pmoad interface is just a hardware level physical connection between AMD KR260 dev board and your Pmod CAN board. Of course you can connect it. Vivado software version has nothing to do with it. After the physical connection is done, what is important is, your FPGA logic should be able to correctly drive those Pmod signals.

Any Pmod extension board can be connected to your AMD KR260 dev board's Pmod interface.

[Query about GPIO pins on 'Development Board, Arty A7-100T'.]

There might be different delays in getting the data from all encoders, i.e. it cannot be guranteed that data from all encoders arrive at the FPGA at the same time.

I would suggest to have a timestamp logic inside the FPGA that will timestamp data arriving in from the various encoders. You also need to have a backstage logic, that sorts these data as per the timestamp already appended to the incoming encoder data. By this mechansim you know which data goes out first and which later. This architecture calls for you append additional data, which you can call header data, to the raw encoder data.

Do you have a system/FPGA architect at your work place? If yes please discuss this with the person and get stuff clarified.

1 - I do not think so, IF I HAVE UNDERSTOOD YOUR INTENTION CORRECTLY.

2- Yes, but as I already said it cannot be guranteeded that you will get data coming in at the same clock edge at all GPIO pins.

3- Yes, why not. You just need to store the encoder data in to a FIFO (maybe multiple FIFOs, depends on a lot of factors and your design) and make that FIFO feed the backend of an Ethernet MAC core.

4- yes, free GPIO pins can always be used for other purposes.

[Any device that can be used as a SPI master at 100 MHz in 1.8V logic?]

5 hours ago, D@n said:

 While the voltage cannot be adjusted while running, it can be set at configuration time and held fixed.

Yes that's what I meant, after the FPGA loads the bitstream and the design is running, the GPIO pin voltages are fixed to either 1.8V or 3.3V  as long as the bitstream is running and the board is not powered off.

I think that is what the OP @thomas1998 wants to do!

[Any device that can be used as a SPI master at 100 MHz in 1.8V logic?]

Really?

For Digilent boards, is it not possible to choose the FPGA GPIO pins to either 1.8V or 3.3V operation as per the designer's wish (using Vivado GUI or TCL)?

Please enlighten me.

[Any device that can be used as a SPI master at 100 MHz in 1.8V logic?]

@thomas1998

As far as I know, you can set multiple FPGA GPIO pins to 1.8V or 3.3V.

You can use the Vivado GUI or use TCL commands to specify the pin constraints.

So in principle you can choose any FPGA, implement SPI Master on the FPGA, set the SPI ports to GPIO 1.8V and connect it with a SPI Slave.

[CMOD A7-35T]

Welcome to the world of technical forums!

When no one answers, it might also mean that finding the answer for the Q is uninteresting or it takes too much effort to find out the right answer (digging in to datasheets, cross-comparing, etc). :-)

[Nexys Video HDMI Pass Through Project]

@digility

Years ago I created a HDMI Passthrough but I had used the zybo z7-10, yours is Nexys, but you just duplicate the idea and change the constraints and some settings.

https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10?_ga=2.217290518.1213385532.1716366440-1444737449.1710929240

Some more help which had helped me to successfully create the project-

 

 

 

[Xilinx successfully programs FPGA, but nothing happens]

@Black-Photon

1. Are you sure that your board is loading the bitstream correctly? Check out for the on-board LED that should light-up after the bitstream is successfully loaded.

2. Next would be to make sure your design/bitstream does what it is supposed to do. And you do that by having a testbench that does behavorial simulation of your design. If you do not have it please make one asap.

3. Even then if <2> is unsuccessful (i.e. you observe that your user LEDs do not light uo as they should or on-board switches do not work), the you need get the Xilinx debug core ILA inside your design and debug your design over the USB-2-JTAG interface.

 

For a deeper understanding, please refer to - 7 Series FPGAs Configuration User Guide, UG470

[ARTY A7-100T Dev Board no longer powers on]

@Philip Davey

I would also try out the 7V-15V power input instead of the USB.

 

[Adding uart 16550 to the block design]

@Luca Frongia

Set those I/O Standard to LVCMOS33 or whatver fits your design rather than keeping them to DEFAULT to solve the problem. Also you have not assigned FPGA pins to those ports. Hence you have those errors as shown in the screenshot.

 

Read more about the TCL command : set_property IOSTANDARD LVCMOS33 [get_ports <your_port_name>]

[Zybo Z7-10 : Accessing the Xilinx FPGA over independent JTAG and not over USB2JTAG bridge]

Problem is now solved.

The FPGA can be detected by the XPC USB II debugger.

I am not using the USB2UART bridge. I just use a separate 5V DC power supply to ensure that the bridge is not activated and the debugger is directly connected to the JTAG signals at J13.

[Zybo Z7-10 : Accessing the Xilinx FPGA over independent JTAG and not over USB2JTAG bridge]

Additionally...

If I change the Jumper at JP5 to set Programming Mode = JTAG (instead of default mode, QSPI Flash), will I be able to see the FPGA as device detected through the JTAG interface (J13) at Vivado Lab?

Is this the way to do it?

 

 

[Would using a USB Hub for UART communication cause any issues?]

It will not be a problem to access ther FPGA over a USB Hub.

Take a look into the Device Driver of your PC, all serial connections to the USB will be separately listed.

[Simulation of the Arty Z7-10 with DDR in VIVADO]

@wayyu,

You can use the DDR3 Control IP core provided by Xilinx.

The Ip is free to use.

Using the GUI of the IP you can select AXI as the user_interface for the Ctrl Core.

There is also the Ctrl IP core documentation, MUST read it. Also there is an example_design in there which you MUST try out before creating your custom design.

[is it okay to connect Zybo z7 PMod ports to digital signals through wires?]

@Michael Bradley

I have not taken a look for a long time into the Zybo Z7 pin mapping file. But I can tell you from memory that the PMOD connections are generally connected to the FPGA GPIO pins, so that you can control them as as you like.

So the answer to your question would be a yes!

[Zybo Z7-10 : Accessing the Xilinx FPGA over independent JTAG and not over USB2JTAG bridge]

Board: Zybo Z7-10

Software: Vivado Lab Edition 2020.2

Debugger: Xilinx Platform Cable USB II

When my Zybo Z7-10 board is connected to the PC using the USB cable, the Software  can detect both the PL and PS. All good here!

It is my desire, not to use the USB2JTAG bridge to access the FPGA over JTAG. Instead, I want to use the J13 header (I have soldered the pins in there for connection) for JTAG connection to access the FPGA. The Xilinx Platform Cable USB II has the JTAG cables at one end and I want to plug these into the J13 to have JTAG access. At the end Software needs to identify the FPGA over this direct JTAG connection.

Is it possible? How can I do it? Is there some jumper settings I must change to facilitate this?

Note that I am still using the USB to power the board, so the USB2JTAG is always remaining activated by default. Should I need to change to a 5V DC adapter to power the board when I want to the JTAG over J13?

I have also referred here -  https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual  but did not find any guidance to activate the JTAG over J13 header.

Please advise.