Aditya Gedela
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Topics posted by Aditya Gedela
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Question: Regarding % and * operations in Vivado using Verilog HDL
By Aditya Gedela, in FPGA
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- 0 votes
- 1 answer
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- 0 votes
- 3 answers
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Question: Problem with Switches and push buttons on Zybo board
By Aditya Gedela, in FPGA
- Awaiting best answer
- 0 votes
- 13 answers
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Question: Displaying a random number on 7 segment display using ZYBO
By Aditya Gedela, in FPGA
- Awaiting best answer
- 0 votes
- 9 answers
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Question: Regarding implementation of queues in vivado
By Aditya Gedela, in FPGA
- Awaiting best answer
- 0 votes
- 3 answers
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Question: Place design Error(During implementation stage)
By Aditya Gedela, in FPGA
- Awaiting best answer
- 0 votes
- 5 answers
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Question: Using $urandom() function in vivado(ZYBO BOARD)
By Aditya Gedela, in FPGA
- Awaiting best answer
- 0 votes
- 6 answers