Ah, yes, the infamous "This page intentionally left blank." page in the Arty schematic...
This page is the interface between the FTDI chip used to implement the Jtag interface to the Artix FPGA. I'm not sure exactly what Digilent is trying to protect here as the schematic is pretty straightforward (I have a schematic for this section of the board. I didn't get it from Digilent--I beeped it out from a dead Arty board and drew the schematic myself).
Please don't ask me for a copy--If Digilent doesn't want to give this info out, they must have their reasons and I'll respect that by not distributing my version.