youxuan

Hi,I have some questions about FPGA. Our development board is Eclypse Z7, and the ADC is Zmod ADC 1410. The environment we are using is VITIS 2019.1. From the official website, we know that the maximum sample rate of the ADC is 100MSPS. Due to our project requirements, we need to lower the sample rate of the ADC. We already know that the sample rate = number of samples / sampling interval time. Originally, we directly reduced TRANSFER_LEN to lower the number of samples, indirectly reducing the sample rate. However, this is not what we want. We hope to directly lower the sample rate and then reduce the number of samples. I asked ChatGPT, and it suggested changing the Sampling Clock, but I couldn’t find any related practical steps online. What methods are available?