yeah the project is targeted for the Artix-7 and not the SoC, thank you!
I'm able to add the PS and routed the fclk to the gp0 clock like you previously stated. I'll edit this reply once I run the bitstream again.
EDIT:
- IT WORKS!!
- Giving FCLK to the GP0_CLK was causing issues so I just gave it an external clock that the entire system was getting.. seemed to not cause any issues but I need to look into why it isn't because its a lil suspicious
- Using the Unified IDE was giving me more pains as well, so I switched to Vitis Classic.
- The BIF file was somehow magically created even though I didn't specify anything so I am going to backtrace my steps to see how that happened
- Otherwise building and targeting the hardware was pretty straightforward and the flash memory was successfully programmed.
Srinivas Sundararaman got a reaction from artvvb in Eclypse Z7 Low-Level Low-Pass Pass Filter Demo Baremetal Boot
