Srinivas Sundararaman

yeah the project is targeted for the Artix-7 and not the SoC, thank you! I'm able to add the PS and routed the fclk to the gp0 clock like you previously stated. I'll edit this reply once I run the bitstream again. EDIT: - IT WORKS!! - Giving FCLK to the GP0_CLK was causing issues so I just gave it an external clock that the entire system was getting.. seemed to not cause any issues but I need to look into why it isn't because its a lil suspicious - Using the Unified IDE was giving me more pains as well, so I switched to Vitis Classic. - The BIF file was somehow magically created even though I didn't specify anything so I am going to backtrace my steps to see how that happened - Otherwise building and targeting the hardware was pretty straightforward and the flash memory was successfully programmed. Thanks for your assistance @artvvb 😃

I don't see the processor that's on the Zynq Board.. As an aside, this is what Vitis Classic gives me:

Hello! I am on Vivado/Vitis v2023.2 I have an eclypse that I am using as a bandpass filter, so I took the low pass demo from the repository and just changed the coefficients. https://digilent.com/reference/programmable-logic/eclypse-z7/demos/low-level-low-pass-filter I can synthesize, implement and generate a bitstream for the board and can also program it through the hardware manager. However I want to load the PL program into the QSPI Flash memory so that I don't have to reprogram the board after a power cycle. I tried many guides on how to do this but I've had no luck so far: https://digilent.com/reference/programmable-logic/eclypse-z7/reference-manual?srsltid=AfmBOoouk23hiDsa5-YBsrhRbN_XkXyTkui_cLVvoEt0wS7VOMOTd7ex https://digilent.com/reference/programmable-logic/guides/zynq-baremetal-boot?srsltid=AfmBOoqrvdjISFWzOZvFnWkvWUNaWGBJNIuMutBl-GdTKEupPuqUn3Pp https://www.adiuvoengineering.com/post/microzed-chronicles-introducing-vitis-unified-ide?_ga=2.64757036.2037215552.1724693711-2102813413.1724370144 https://docs.amd.com/r/en-US/ug1283-bootgen-user-guide/Launch-Bootgen-GUI https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/439124055/Zynq-7000+FSBL So far I have been generating the bitstream, and exporting the hardware (XSA) with the bitstream included and bringing it to Vitis to use the Bootgen GUI to generate the bin file. HOWEVER, once importing the XSA into an application platform, it doesn't show any processors in the drop down. The invalid platform shows up on the Unified IDE, and Vitis Classic just says I haven't a valid processor but there isn't any in the dropdown I think the problem boils down to the fact that the project itself doesn't have the PS Cortex ARM chip block in the vivado project, and so consequently Vitis doesn't have any listed. The question then is: Can I load this project in non volatile memory to be able to boot it on power and I'm missing something? Or is there a way to add a arm chip to the project somehow? I'll attach the XSA I'm using for reference bandpassfilterhardware.xsa