pollostrazon

Good morning, I tried and searched up for other questions related to the matter but I did not manage to find a way out of this. I have implemented my design with an ILA with 19 ports and 1024 depth. I have also tried with smaller ILAs, thinking maybe the error was due to not having enough logic cells, but it persists. I am working on a Genesys 2 (xc7k325t...) and the same code was working fine on a KCU116 (xcku5p...). At the implementation, I get the message: ============================ INFO: [Labtools 27-1434] Device xc7k325t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3361] The debug hub core was not detected. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. 2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). WARNING: [Labtools 27-3413] Dropping logic core with cellname:'ila_probes_inst' at location 'uuid_2BC77ADE63DF5439B550E898476868A8' from probes file, since it cannot be found on the programmed device. ======================= I have tried and followed the step 1. and 2. but nothing changed. I have also tried to set up a clock reserved to the ILA through the clocking wizard, to be sure it was free-running, but nothing changed still. Can someone give me a direction? Maybe I am missing something. I am currently avoiding the ILA in the design. Thank you all in advance. Paolo