Heya Art,
Thanks for the sanity check. I did find the work-around also -- going through the clock wiz IP. I am a sw/fw monkey, and I am learning fpga as a side thing, but it looks like the clock source is hooked up fully after a successful 'Generate Bitstream'. (Before generating BS, the block design Signal tab still showed it disconnected.) Maybe this is a 2024.1 feature.
But, even if it is a bug, I'm reluctant to go to an older version now that there seems to be a work-around. Meh, trading one set of broken things for another ...
I was mostly able to step through the metal guide -- but there seems to be a conflict with the 'manually constrained via the master xdc' workflow for adding BUTTONS gpio. The U18 pinned [0]th button seems conflicted with reset. I don't feel like that rabbit hole now, and just replaced that example with the preset 4-bit button selection. That's good enough for now -- i really just want to make a full iteration all the way through Vitus.
Anyhow, I have an Okay bitstream now, so on to the next step. Thanks, Owen