NGUYENTRUNGHIEU

Dear Arthur,
I would like to thank you having spent your time to reply my question and your great comments. Because of people like you, beginers as me can progress! Your comments are very helpful!
Have a good day and many thanks again!
Trung Hieu

Hey @NGUYENTRUNGHIEU
Your location constraints are missing the trigger_3 port - please review your warnings, critical warnings, and errors in Vivado, there might be something about an unconstrained port. In general, you should review these messages regardless.
I haven't built your sources myself to check errors (just takes time...), but some assorted comments on your code:
The tools may or may not optimize the multiply and divide here, but if they don't, I might be concerned about meeting timing, which would generate critical warnings if failed. The same operation can be done using bit shifting and concatenation - "{wb, 1'b0}" is equivalent to "2 * wb" for example. You might also want to simulate the differences in results when replacing "(2*wb+1)/2" with "wb" - they ought to be the same results...
Also, mixing "LED <= DELAY" in here alongside blocking assignments is a potential issue. Mixing them is just best avoided: https://nandland.com/blocking-vs-nonblocking-in-verilog/. There's probably an inferred latch in this block - combinatorial blocks should usually cover all edge cases - edit: this can be spotted at a glance from these always blocks missing "else" statements.
Similarly, using nonblocking assignments in a combinatorial block could be an issue, due to inferred latches - based on trigger_start being used as an enable pin later down in the source, it seems you intend its "1" state to be held for more than one clock cycle. It potentially does in simulation, because of the implied latch, but that's not good practice in synthesis - if something needs to hold a value for more than a clock cycle, without something else its derived from to hold that value for it, it needs to be clocked. In this case, neither timer_start nor trigger_rising are clocked, and trigger_rising only holds its value for a single cycle. Things working in simulation are probably due to issues with the coding style that lead to the aforementioned latches...
Looking into both the differences between combinatorial and sequential logic (and therefore the underlying digital circuits you're describing through your HDL) and the differences between blocking and nonblocking assignment in Verilog would be recommended.
Hope this helps,
Arthur