Will Creek

Thanks for responding. We have made the decision to go with a different option, but we will keep this in mind for future products. Will

My Company is looking at the CMOD A7-35T as a way to drive an evaluation board and give our customers an FPGA reference design to use with our custom IC. The problem is that we need 1.8V 800Mbps+ DDR signals. We need both input and output signals. All of the CMOD IO pins are 3.3V Looking at the schematic of the CMOD and the PCB it looks almost impossible to reconnect the IO banks to 1.8V instead of 3.3V. The power pin connections are internal to the PCB. Also, it would be easy to modify the 3.3V supply to 1.8V with a resistor change, but the onboard SRAM and EEPROM will not work at 1.8V. So, we are forced to lay out our own version of the board. We have a schematic, but would have to create a PCB layout. We only need 50 - 100 boards, so it will probably cost more to make our own than buy them, but it's that or use the competitor's FPGA. Two questions: Is the schematic complete? I am particularly concerned about the EEPROM and bootstrap circuitry. Can we get a layout file of the PCB to save us some time? We would of course sign NDAs promising not to sell it. The last question is in the category of "it doesn't hurt to ask". I see that others have asked the IO voltage question before. There are not many 3.3V applications left outside of the hobby world. If you are looking for a cheap project modification to sell a lot more boards, programmable voltage IO banks feels like a great opportunity. Upgrade the RAM to DDR3 while you are at it. Of course the real reason to have evaluation boards is to really show off the FPGA parts. The Artix 7 family is seriously hobbled by only being able to evaluate it with an IO standard from the last century.