I'm trying to do a project that PL can read/wrtie DDR3 with High performance AXI interface of ZYNQ on my Arty Z7-10, and I want to know is there an IP for the DDR IS43TR16256A-125KBL(which is the DDR3 used in Arty Z7-10) so I can simulate my design with HDL wrapper on vivado.
Simulation of the Arty Z7-10 with DDR in VIVADO
in FPGA
Posted · Edited by wayyu
Hi
I'm trying to do a project that PL can read/wrtie DDR3 with High performance AXI interface of ZYNQ on my Arty Z7-10, and I want to know is there an IP for the DDR IS43TR16256A-125KBL(which is the DDR3 used in Arty Z7-10) so I can simulate my design with HDL wrapper on vivado.
Since I don't find this kind of resource that can used for simulation on https://www.issi.com/US/Index.shtml
If anyone know where to find it, it will be a lot of help for me, thanks.
Wayyu