[Arty Z7 DDR simulation problem]

Hello

 

I'm currently working on a project with a lot of access to DDR on my board, and I'm trying to run simulation to know if my design is work.

Since the there's a DDR controller inside the ZYNQ, I use MIG to generate a memory interface and use ddr module in it's example design, but the simulation result shows that the DDR module's signal is all Z.

So I'm wondering if there a way to just use my ZYNQ DDR configuration to generate a ddr module for simulation?

Or did Digilent provide ddr module or MIG configuration that matches my board.

Thanks everyone!!!

[Simulation of the Arty Z7-10 with DDR in VIVADO]

Hi

I'm trying to do a project that PL can read/wrtie DDR3 with High performance AXI interface of ZYNQ on my Arty Z7-10, and I want to know is there an IP for the DDR IS43TR16256A-125KBL(which is the DDR3 used in Arty Z7-10) so I can simulate my design with HDL wrapper on vivado.

Since  I don't find this kind of resource that can used for simulation on https://www.issi.com/US/Index.shtml

If anyone know where to find it, it will be a lot of help for me, thanks.

 

Wayyu