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Dharmendra

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    Dual core Application in Genesys -ZU in Vitis 2023.2

    in FPGA

    Posted · Edited by Dharmendra

    I am working in Vitis 2023.2 and Genesys ZU (zynq mpsoc +ultrascale device) .Basically i want to create dual core application .I have made Platform project and added domain for both core 0 and core 1.Then i created system project .I have updated linker script also .but at last, the application for core 0 only running .

    Extraction of Harware block design information from default out-of-box image in GENESYS ZU 5EV.

    in FPGA

    Posted

    I am working in Genesys ZU 5EV board with boot mode selected as SD card. this SD card comes with default petalinux out-of-box image .I am curious to know from which hardware file (.xsa) file this image is made up of.I went through Github and got "system.xsa" file. but i dont know how to extract block design information from this file . Basically i want to do reverse engineering and make block design from .xsa file with the help of vivado.

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