[Genesys 2 HDMI Demo Modification Issues]

I am trying to modify the HDMI Demo to do some video processing (scaling and image rotation).

My issue is that one I export hardware and Update Hardware Specification, I cannot get Vitis to build the SW application. I have also tried unsuccessfully to export and build the provided floorplanner project without any changes. 

The SW provided for the demo works fine, but I can never build from the Vivado generated .xsa file. I can build successfully using the Xilinx platforms, but none of them are for the Genesys 2 or Kintex-7.

The Vivado end seems to be fine--all my problems start over on the Vitis side. The "Update Hardware Specification" seems to go smoothly, but when I try to build the application, I get an error telling me that error files are missing. When I look at the Explorer window in Vitis, I can see that many files are missing.

There is a lot of traffic online about problems very similar to this, and I have tried all of the remedies I can find, but none of them do anything to solve the issue I'm having.

Can anyone provide any guidance here?

I'm using:

• Vivado ML Enterprise v2023.1.1, 64-bit, with the OEM_7K325T_DesignEd license that comes with the Genesys 2 voucher
• Vitis IDE v2023.1.0 (64-bit)

[Genesys 2 HDMI Demo]

15 hours ago, JColvin said:

Hi @DBanks60,

I don't have a Design Edition installed, but my understanding is that as long as the Design Edition allows bitstream generation for the correct Xilinx chip (I haven't checked, but I don't think vouchers for Design Editions differentiate between speed grades or something like that), then it should work.

There should not be any additional, paid IP that is required to run the HDMI demo, https://digilent.com/reference/programmable-logic/genesys-2/demos/hdmi.

Let me know if you have any questions.

Thanks,
JColvin

Thanks https://forum.digilent.com/profile/5-jcolvin/.

We have progressed through the hardware design at this point, and I'm confident that the Design Edition we are using (OEM_7K325T_DesignEd) is working fine, allowing all of the IP to build--we can synthesize, implement, and create bitstream.

We have also been able to run the HDMI demo described in  https://digilent.com/reference/programmable-logic/genesys-2/demos/hdmi.

We're now having issues with the build in Vitis. Looking at https://digilent.com/reference/programmable-logic/guides/vitis-update-hardware-specification, we're getting stuck in that last paragraph:

"Changes to the software application may be required before the application can be built and programmed onto the board, however, detailing what may need to be done is outside of the scope of this guide."

We want to add modules to the hardware design, but when we do, everything works fine on the Vivado side, but on the Vitis side, when we Update Hardware Specification and then try to build the videodemo_system, we get errors.

I believe that the errors happen because Vitis is not updating correctly. When I compare the previously working workspace to the new one, there are header files that disappear.

I see posts on online forums that addressed this issue in the past, involving modifying or resetting BSP, but none of those efforts to fix this issue are working for me now.

[Genesys 2 HDMI Demo]

Does anyone know if the Genesys 2 HDMI Demo works with Vivado OEM Kintex-7 FPGA XC7K325T Vivado Design Edition (OEM_7K325T_DesignEd) installed?

[Using DDR as a Video Frame Buffer]

On 8/4/2023 at 6:37 PM, zygot said:

Great! Thanks for the feedback. Hopefully, you can see the basic functionality as a starting point for more interesting projects.

Would you have any advice to offer on how to replace your dpti module with dvi2rgb to implement a hardware HDMI-in source solution?

[Using DDR as a Video Frame Buffer]

Thanks for all of your help-I have it working on a Genesys2. [I edited and erased my questions]

[Using DDR as a Video Frame Buffer]

Great project!

Please clarify some things for me concerning the readme file you provided. (1) I need to compile VideoDemo.cpp--there is no executable for this until I do, yes? (2) Once I have that executable, I can proceed with adding the Digilent ADEPT SDK dpti and dmgr libraries and headers to the project, implement the project, create the bitstream and program, and then execute the windows command line with the board connected to see the turkey image, right?

In other words, the parts about using GIMP and a hex editor, you already did, correct?

[Using DDR as a Video Frame Buffer]

2 hours ago, zygot said:

@DBanks60

No, I haven't installed Vivado 2023.1. The demo tried to avoid version issues by providing commentary about how to re-create the IP in whatever version of the tools anyone might be using. Occasionally, Vivado makes changes that thwart even this approach.

Have you encountered a problem building the project in Vivado 2023.1? The MIG IP, in my experience, can be difficult depending on what version of the tools you are using. Specifying the target as a Genesys2 in your project settings instead of using the device product number is, in my experience, a good way to get all kinds of IO constraint artifacts that cause problems and have to be manually corrected. I've stopped using the board files many versions of Vivado ago. Be aware that older versions of the Digilent master constraints files have numerous errors. The schematic is golden as far as I can tell. I'm in the habit of checking the constraints against the schematic whenever I use pin for the first time.

[edit] The main reason why I don't use current versions of Vivado for Genesys2 projects is because my device license isn't supported by them.... I still use a LOT of vendor tool versions, on way too many PCs, for one reason or another. Sigh....

Thanks. No problems yet--I have not started my project, since I don't have a Genesys 2 board yet. Once it have the board, and the IP voucher for Vivado ML Enterprise, I'll get started. Your code is very well commented, thanks for that!

[Using DDR as a Video Frame Buffer]

Have you tried your Genesys2VideoDemo_R1 with Vivado 2023.1?