It supports up to 12 MBaud, and is in fact usually used with 12 MBaud.
In test benches it allows even 120 MBaud, which speeds to the simulation time of full systems.
It is usually used with FIFO buffering and separate system and serial clock domains (see serport_2clock2.vhd).
It can of course be used in a simple single clock domain setup (see serport_1clock.vhd).
UART Transmitter with BASYS 3
in FPGA
Posted
Hi,
within the w11 project you'll find among many other things
The UART features
It supports up to 12 MBaud, and is in fact usually used with 12 MBaud.
In test benches it allows even 120 MBaud, which speeds to the simulation time of full systems.
It is usually used with FIFO buffering and separate system and serial clock domains (see serport_2clock2.vhd).
It can of course be used in a simple single clock domain setup (see serport_1clock.vhd).
Cheers, Walter