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tommienator

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  1. tommienator's post in Zedboard - Vivado 2020.2 was marked as the answer   
    Hey @JColvin,
    Thanks for the response. Considering the board file, indeed I've taken the one from Digilent (assumed this was the maintained one since Avnet didn't provide support anymore but Digilent does (read this on a certain forum post). Nevertheless, first followed your advise and installed the board file directly from Avnets Github page (bdf/zedboard/1.4 at master · Avnet/bdf · GitHub), which should, accordantly to the commit messages, support Vivado 2020.2. But this is for revision D I've noticed.
    Nevertheless, this didn't resolve the problem. Just double checked the revision, and the board is revision E.
    Considering the SD card project, there was an SD card delivered with the Zedboard which contained a Linux image. If you go on the Digilent website and search for the images that are present then you'll see the SD card being delivered with the board (https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/).
    Just double checked if nothing was wrong with the Zedboard so I've thrown on an custom IP for the UFMT600X board that is connected via the FMC header and using that as a data streamer (via USB30.) towards the PC (without any Zynq instantiation, so the data generator + FIFO USB3.0 bridge where implemented as custom logic) and that worked just fine so I guess there is nothing wrong with the FPGA itself. 
    I came across another post where the person had the same problem with revision E boards (https://forum.digilentinc.com/topic/20531-zedboard-rev-e/), so is there a possibility to get an revision E board file and test it?
     
    // Edit --> SOLUTION
    Just founded this document from a previous thread here on the forum and since the memory parts on the Zedboard are of 4Gb  (https://zedboardupgrade.s3.us-east-2.amazonaws.com/ZedBoard+Rev+E+project+update+procedure.pdf?_ga=2.197137327.1072668274.1623081646-1457440089.1620987456). This resolved the problem, thus is there a board file for revision E available or are the memory components not instantiated via the board design and this wouldn't resolve anything? A permanent fix would be nice for this :-)?
     
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