Just over a third of the way down the page the tutorial starts talking about the AXI GPIO IP. This sentence has me lost:
Quote
As can be seen, the individual ports that make up the interface are named <interface>_tri_i, <interface>_tri_o, and <interface>_tri_t. When constrained to tristate buffers, the bus that is connected to FPGA ports is named <interface>_tri_io.
I do not understand where this naming is coming from ("As can be seen"). On the diagram the AXI GPIO ports are labelled gpio_io_i, gpio_io_o and gpio_io_t. I cannot find any reference to ***_tri_io.
Help with Zynq tutorial
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I need a little help understanding this tutorial: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi
Just over a third of the way down the page the tutorial starts talking about the AXI GPIO IP. This sentence has me lost:
I do not understand where this naming is coming from ("As can be seen"). On the diagram the AXI GPIO ports are labelled gpio_io_i, gpio_io_o and gpio_io_t. I cannot find any reference to ***_tri_io.
Any pointers appreciated!