Hi @JColvin,
I changed the code in the .xdc based on your recommendations of putting the space between -dict and the first curly bracket, and also naming the ports based on my Verilog port definitions as shown below:
module top(
input clk_100MHz, // basys clk signal
input reset, // btnC on basys
inout TMP_SDA, // i2c sda on temp sensor - bidirectional
output TMP_SCL, // i2c scl on temp sensor
output [0:6] SEG, // 7 segments of each display
output [3:0] AN, // 4 anodes of 4 displays
output [7:0] LED // basys leds = binary temp in deg C
);
##Pmod Header JC
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {TMP_SCL}]
#set_property IOSTANDARD LVCMOS33 [get_ports {TMP_SCL}]
set_property -dict {PACKAGE_PIN N17 LVCMOS33 PULLUP TRUE}[get_ports {TMP_SCL}];
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {TMP_SDA}]
#set_property IOSTANDARD LVCMOS33 [get_ports {TMP_SDA}]
set_property -dict {PACKAGE_PIN P18 LVCMOS33 PULLUP TRUE}[get_ports {TMP_SCL}];
And,
Synthesis runs OK.
Implementation runs OK.
Bitstream Generation not so much. The following are the critical warnings and errors generated:
[Designutils 20-970] Unrecognized or unsupported command 'set_property -dict {PACKAGE_PIN P18 LVCMOS33 PULLUP TRUE}[get_ports {TMP_SCL}];' found in constraint file. ["C:/Users/david/FPGA_Vivado_Designs/Temp_Sensor_Basys3_PmodTMP2/Temp_Sensor_Basys3_PmodTMP2.srcs/constrs_1/new/const_temp_sensor.xdc":63]
[DRC NSTD-1] Unspecified I/O Standard: 2 out of 23 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: TMP_SCL, and TMP_SDA.
[DRC UCIO-1] Unconstrained Logical Port: 2 out of 23 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: TMP_SCL, and TMP_SDA.
Thank you JColvin for helping with this. Please, advise as to what to do next.