FPGA4Life

Sorry for the confusion with the spaces. Thanks for letting me know. I fixed it, and it works. The Basys 3 and PmodTMP2 work great. Thanks very much to you and JColvin for solving this problem.

Hi @JColvin, I changed the code in the .xdc based on your recommendations of putting the space between -dict and the first curly bracket, and also naming the ports based on my Verilog port definitions as shown below: module top( input clk_100MHz, // basys clk signal input reset, // btnC on basys inout TMP_SDA, // i2c sda on temp sensor - bidirectional output TMP_SCL, // i2c scl on temp sensor output [0:6] SEG, // 7 segments of each display output [3:0] AN, // 4 anodes of 4 displays output [7:0] LED // basys leds = binary temp in deg C ); ##Pmod Header JC ##Sch name = JC3 #set_property PACKAGE_PIN N17 [get_ports {TMP_SCL}] #set_property IOSTANDARD LVCMOS33 [get_ports {TMP_SCL}] set_property -dict {PACKAGE_PIN N17 LVCMOS33 PULLUP TRUE}[get_ports {TMP_SCL}]; ##Sch name = JC4 #set_property PACKAGE_PIN P18 [get_ports {TMP_SDA}] #set_property IOSTANDARD LVCMOS33 [get_ports {TMP_SDA}] set_property -dict {PACKAGE_PIN P18 LVCMOS33 PULLUP TRUE}[get_ports {TMP_SCL}]; And, Synthesis runs OK. Implementation runs OK. Bitstream Generation not so much. The following are the critical warnings and errors generated: [Designutils 20-970] Unrecognized or unsupported command 'set_property -dict {PACKAGE_PIN P18 LVCMOS33 PULLUP TRUE}[get_ports {TMP_SCL}];' found in constraint file. ["C:/Users/david/FPGA_Vivado_Designs/Temp_Sensor_Basys3_PmodTMP2/Temp_Sensor_Basys3_PmodTMP2.srcs/constrs_1/new/const_temp_sensor.xdc":63] [DRC NSTD-1] Unspecified I/O Standard: 2 out of 23 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: TMP_SCL, and TMP_SDA. [DRC UCIO-1] Unconstrained Logical Port: 2 out of 23 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: TMP_SCL, and TMP_SDA. Thank you JColvin for helping with this. Please, advise as to what to do next.

Thank you JColvin for helping me to solve this problem. Below is what I put in the .xdc based on your port modeling recommendation. I did alter the top module and any necessary signals therein to reflect the ports name changes. The commented lines are the original port declarations from the Basys 3 master xdc and show the correct Artix-7 pin# for use with PmodTMP2 on JC. ##Pmod Header JC ##Sch name = JC3 #set_property PACKAGE_PIN N17 [get_ports {TMP_SCL}] #set_property IOSTANDARD LVCMOS33 [get_ports {TMP_SCL}] set_property -dict{PACKAGE_PIN N17 LVCMOS33 PULLUP TRUE}[get_ports {scl}]; # line 59 ##Sch name = JC4 #set_property PACKAGE_PIN P18 [get_ports {TMP_SDA}] #set_property IOSTANDARD LVCMOS33 [get_ports {TMP_SDA}] set_property -dict{PACKAGE_PIN P18 LVCMOS33 PULLUP TRUE}[get_ports {sda}]; # line 63 The results are: Synthesis runs OK. Implementation runs OK. Generate Bitstream not so much. Below are the error messages. First 2 are "Critical Warnings", and last 2 are "Errors". [Common 17-170] Unknown option '-dict{PACKAGE_PIN', please type 'set_property -help' for usage info. ["C:/Users/david/FPGA_Vivado_Designs/Temp_Sensor_Basys3_PmodTMP2/Temp_Sensor_Basys3_PmodTMP2.srcs/constrs_1/new/const_temp_sensor.xdc":59] [Common 17-170] Unknown option '-dict{PACKAGE_PIN', please type 'set_property -help' for usage info. ["C:/Users/david/FPGA_Vivado_Designs/Temp_Sensor_Basys3_PmodTMP2/Temp_Sensor_Basys3_PmodTMP2.srcs/constrs_1/new/const_temp_sensor.xdc":63] [DRC NSTD-1] Unspecified I/O Standard: 2 out of 23 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: scl, and sda. [DRC UCIO-1] Unconstrained Logical Port: 2 out of 23 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: scl, and sda.

Hello everyone! My name is David, and I am so excited to have found this forum and be a part of it. I am a huge fan of Digilient products and own, or have owned, the Basys 3, Nexys A7-50T, Nexys Video, Cora Z7 with 7010, Zybo Z7 with 7020, Cmod A7, Analog Discovery 2, and a plethora of PMODs including Keypad, Temp Sensor, Rotary Encoder, Accelerometer, OLED, and many more I cannot remember them all. I fell in love with digital design during college and learned the Verilog language and FPGA programming all on my own. I have had some successes and some failures, but I just keep going.

Hello, I have a Nexys A7-50T that includes the ADT7420 temperature sensor. I created a circuit using Verilog and successfully read the Celsius temperature data from the sensor and displayed it on 7-segment displays and LEDs. I also have a Basys 3 and the PmodTMP2, which has the exact same sensor, the ADT7420, found on the Nexys A7 and uses the same I2C interface, and the default address 0x4B is exactly the same with jumpers J1 and J2 of the Pmod 'OPEN', which is how the PmodTMP2 comes in its package, which I very recently purchased from the Digilent store. The same Verilog files were used, but with a different .XDC file tailored for the Basys 3 using Pmod JC to connect the PmodTMP2. The resulting value on the 7-segment display is 00 for the temperature. The circuit is working, and a value is being driven from the sensor on the Pmod, but the value is not correct. The PmodTMP2 has the same exact IC as on the Nexys A7, the only difference is the Nexys has dedicated pins connecting the Artix-7 to the ADT7420, whereas using the Basys 3 with PmodTMP2 the connection from Artix-7 to ADT7420 is through a Pmod connection. A circuit that works on the Nexys A7 should also work with the Basys 3/PmodTMP2 combo in all logical respects. Why would the Basys 3/PmodTMP2 combo not be working properly and only showing a temperature of 00? Any help here would be greatly appreciated.