Pulse

Hi, @rmccormack1 Here are my two cents based on my experience with Digilent Arty A7-100T board. The board file provided by Digilent will set the sys_clk of mig7 to be "Single Ended". In this case, the sys clk of mig 7 will have to connect to FPGA clock pin directly. The error above will occur if you generate the sys clock from mmcm, To fix that, you can reconfig the mig 7 and set the sys clk to be "No Buffer". Thanks! FpgaPulse (https://fpga.pulserain.com)