[How can I reset the Arty-S7 board via command from USB/UART ?]

Sorry for the threw off 😇

I was not familiar with Digilent Adept Utilities so thanks for that.

[How can I reset the Arty-S7 board via command from USB/UART ?]

Hi 

The behaviour I'm looking for is this:

1. Send a command from a PC host.

2. The FPGA will get configured from a valid bitstream via SPI Flash.

(You can assume the bitstream is already flashed) 

 

Thanks!

[How can I reset the Arty-S7 board via command from USB/UART ?]

Thanks,

I understand the difference between reset and configuration/programming.

I wanted to mimic the behaviour of pressing the physical reset or reprogram buttons, from a host PC.

I guess reprogramming with JTAG is the only to achieve that.

[How can I reset the Arty-S7 board via command from USB/UART ?]

How can I reset the Arty-S7 board via command from USB/UART J10 Connector?

Do I need to use Vivado?

Can it be done without using Vivado?

I basically want to reset the FPGA so it will be programmed again using the SPI-Flash JP1 jumper set to SPI.

 

Thank you!

[Looking for a UART programmable logic example project for Arty S7 with Vivado 2022.2]

Thanks JColvin,

So the Xilinx IPs like UART 16550 and AXI UART Lite don't add any value beyond the code from nandland you sent?

What about double buffer implementation? where can I find something similar which supports the UART code?

 

 

[Question about vivado board files]

Hi JColvin

I understand, we'll just have to wait for Xilinx to come up with a solution.

I'll stick with downloading the XDC files manually.

Thank you very much for the inquiry.

 

[Looking for a UART programmable logic example project for Arty S7 with Vivado 2022.2]

Thanks JColvin!

I was able to port the GPIO example to Vivado 2022.2 and used the Arty-S7 PMOD (JA) connector to send data to a PC connected to the PMOD using an FTDI (TTL/USB).

I would like to proceed with the vhdl based UART example (not Microblaze) and expand it into an end-to-end request response design.

The Arty fpga should support both RX and TX, store the incoming data into a buffer, analyse it and send a response respectively.

I that there ready to use IPs from Xilinx. Not sure how flexible are they.

Should I just expand your example and build my design around it?

What is your suggestion to proceed with this issue?

 

Thanks again!

 

[Looking for a UART programmable logic example project for Arty S7 with Vivado 2022.2]

Thanks JColvin for the clarification, I will give that demo a try!

Is it possible to do a UART loop-back wiring between two Pmod connectors, without the Pmod RS232/RS485?

Thanks again!!

[Looking for a UART programmable logic example project for Arty S7 with Vivado 2022.2]

Thank you James for the answer.

First, perhaps I was not that clear.

I do not need both RS232 and RS485 working on the same RX and TX pins, they can be on separate PMOD connectors and thus different logic signals.

I want to start with RS232.

Is there a VHDL UART code example (not Microblaze based IP) for working with PMODs? specifically the  Digilent RS232?

 

Also, I see in the The Digilent Pmod RS232  description page a note which states:

 

Quote

Note: There are two UART signal pin assignment conventions in use on Digilent products. This product uses the old signal assignment convention. Connecting a product using the old convention with one using the new convention requires the use of a UART Crossover Cable (not included). Click here for a more detailed explanation.

 

Can use the Pmod RS232 with the Arty-S7? do I need to use the Crossover Cable?

 

Thanks!

 

 

[Question about vivado board files]

Hi all and thanks for the replys.

I understand that the XDC file has to be added manually and I also followed the instructions for adding it successfully.

I was asking why they're not being added automatically while choosing the board type in Vivado project creation.

I assume the reason was described by JColvin regarding some Xilinx restrictions.

[Hello Digilents!]

Thank you!

[Hello Digilents!]

Hi All

I'm Roy and I'm working on the Arty S7 and the Zybo Z7-20!

Good luck to you all!

[Question about vivado board files]

Hi

Just out of curiosity, why are the Digilent Xilinx Design Constraint (XDC) files are not part of the vivado-boards git repository, and can be selected when adding a constraint with the appropriate board type?

Why do I have to download the XDC file from a separate digilent-xdc repository?

When I create a new project in vivado and choose the board type, the board's configuration files are added to the project (XMLs), why is the XDC file not one of them?

Thanks!

[Looking for a UART programmable logic example project for Arty S7 with Vivado 2022.2]

Hi 

I'm looking for a full example project, for using UART communication over the PMOD connectors (preferably all 4) and not over the USB-UART Bridge.

It should support both of these Pmods:

Pmod RS232

Pmod RS422/485

 

I'm using the Arty S7 (50) with Vivado 2022.2 on Linux.

Thanks!