dbartlett

Hi, I am working on an FPGA design that is based around the Artix 7, we are using your A7 Board as a development kit for the firmware aspects. I intend of using boundary scan as part of our test plan and want to create a base project around the A7 board so I can plan the common parts of the testing. Would it be possible to provide a Netlist file and BoM for the A7 kit? I can technically create this manually from your schematic but it would be really, really tedious. Thanks in advance!