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The circuit board is Eclipse Z7. The circuit generates an arbitrary waveform with a DAC (Zmod1411) and receives it with an ADC (Zmod1410-105). I want to get the maximum and minimum values of data acquired by ADC within a certain interval. What kind of circuit should I use to implement this on PL? We have already been able to retrieve the data output from the UART. Please let me know if there is a better way.

I tried the zmod sample program on vitis2022.2, but I got the following error. What is causing this? Also, how can I solve it? error: ordered comparison of pointer with integer zero ('FlashEnv*' {aka '_flash_env*'} and 'int') file:flash.c program: ------------ FlashEnv *flash_env = (FlashEnv *)malloc(sizeof(FlashEnv)); if (flash_env < 0) { return XST_FAILURE; ------------ Thank you.

Do you have a sample project using Zmod scope controller IP & Zmod AWG controller IP? I want to run it with Vivado2022.2. Past IPs could not be made to work. Please let me know if you have that project.

@芸術品 Thank you for your answer. I will try the method you told me.

I'm trying to get Pmod AD1 working with Cora-Z7-10. However, Generate Bitstream fails with the error code below. When I checked the forum, it seems that the cause is that the IP core update has stopped.Is there a sample program that uses GPIO instead? Also, is there any other way to deal with it? Thank you. [DRC NSTD-1] Unspecified I/O Standard: 8 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. _io, and ja_pin9_io. [DRC UCIO-1] Unconstrained Logical Port: 8 out of 138 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ja_pin10_io, ja_pin1_io, ja_pin2_io, ja_pin3_io, ja_pin4_io, ja_pin7_io, ja_pin8_io, and ja_pin9_io. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.