[How to Reconfigure AXI IIC IP in xilinx Vivado for external IR temperature sensor]

Hi @artvvb, I have done some modification in the block design and in constraint file , Please find it with the attachment, The bitstream generation is succesfull, but I am not sure either pin mapping is correct or not, if I dont include any constraint file, yet bitstream generation succeds. So I am confused. Would you please tell me how can I be sure that pin mapping is correct? When bitstream generation failed, it showed which pin to map, according to this I wrote the constraint file. I am also not sure, should I write any constraint file regarding VCC,and GND ? or leaving it as it is will be just fine?

[How to Reconfigure AXI IIC IP in xilinx Vivado for external IR temperature sensor]

Edit: Customer hid original question and deleted original post text, didn't notice in time so the original text is lost :/