btremaine

UPDATE: My original problem was that I was not meeting the timing requirements with a 100Mhz clock in a 15-bit down counter, or even an 8-bit down counter. The total timing slack was about -4.5nsec. This was running the external pin 100MHz into a down counter. What I learned was that running the external 100MHZ into an MMCM with a 100MHz output routes the clock signal through a special 'array' optimized for clock timing. I used the MMCM 100MHz output to run my 15-bit down counter and now achieve a total timing slack of +6.07nesc. I did not need to generate 100kHz at the MMCM output; a 100MHz output with the down counter did the trick. I also did not need to use the create_generated_clock command or create_clock command. I only used the pin assignment: set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ] Thanks to all who contributed suggestions. I would suggest reading the ug472-7Series_Clocking.pdf app note. ug472_7Series_Clocking (1).pdf

Thanks for your response. I am aware that the create_generated_clock is only for setting constraints for static timing. I considered using an MMCM but the IP generator wizard would not accept an output of 100kHz with an input of 100MHz. The minimum output allowed was very much larger (>1Mhz). In this case, is it feasible or even advisable to cascade MMCM's? Seems like a waste of resources. The 100kHz clock is used for a seven-segment LED display in which I'm using a 120Hz refresh rate. In this application, the jitter between the CLK100MHZ and the 120Hz refresh rate is not of important. I was trying to give the synthesis guidelines on the timing and avoid warnings of 'bad practice'. Thanks,

I'm fairly new at FPGA code and am trying to develop Verilog code for a Basys 3 board using Vivado. For several days I have struggled with getting the 'create_generated_clock' command to work. I have a large program but reduced it to a simple divider and want to declare the Q output of a DFF as a generated clock. The program passes behavioral sim with a test bench as well as synthesis and implementation with no errors. A warning in the Report Methodology reports 'TIMING #1 Critical Warning The clock pin Led_reg.C is not reached by a timing clock' The clock commands I have in my XDC file are: create_clock -period 10.000 -name sys_clk -waveform {0.000 5.000} -add [get_ports CLK100MHZ] create_generated_clock -name Q_out -source (get_pins Q_out_reg/C ) \ -divide_by 8 (get_pins Q_out_reg/Q ) The ultimate source is the CLK100MHZ coming in on an external pin. Do I have an error in my command for create_generated_clock? My intent was to specify Q_out as the generated clock and CLK100MHZ as the source, but I have some confusion in using Vivado to identify the net, source, or port to use in the command. Using the TCL command report_clocks shows only the 100MHZ clock; Clock Period(ns) Waveform(ns) Attributes Sources sys_clk 10.000 {0.000 5.000} P {CLK100MHZ}