Hi,
I'm running the basic hello world program with Revision E zedboard. I'm only using PS part using Zynq processor with vivado 2020.1 and using vitis 2020.1 for creating platform and application project. Somehow when I try to run the program and see the output in vitis serial terminal I see garbage output. I'm using diligent board files for zedboard from the git repository and I'm using "MT41K256M16 RE 125" as DDR configuration as I have FPGA Rev E board with FBGA code that supports this config. Can some help me with this why I see garbage output
