DLin

I have a custom board with 1 x XCVU7P FPGA. With a Xilinx Platform Cable, I don't see any issues programming a bit file or detecting the target at any frequency. When I use a Digilent JTAG-HS3, I can only reliably program and detect the target at 30 MHz. However, the Virtex US+ datasheet specs max TCK frequency as 20 MHz. When I try lowering the TCK frequency to 15 MHz, I sometimes see an End-of-Startup LOW error at the end of programming depending on the JTAG-HS3 (some program successfully, others fail 100% of the time). If I continue to lower the TCK frequency to 10 MHz or lower, on all JTAG-HS3s with multiple boards, I no longer am able to reliably detect the target. 1. Have you ever seen an issue like this with the Digilent JTAG-HS3 where lower TCK frequencies lead to target detection or programming failures? 2. Do you have any suggestions of what JTAG instructions to look for to debug this failure? Signal quality of the TCK, TMS, and TDI look good going to the FPGA with no setup/hold violations. TDO signal integrity back to the JTAG-HS3 is also good with no setup violation.