LLL

As artvvb points out [Thank you very much], the low-level Scope IPs data sheet lists a minimum sampling clock frequency of 10 Msps. That probably is low enough for my application. But as I read the IP data sheet, it says that the minimum sampling clock frequency is enforced by me, not by the IP, so (at least in theory) I can set it lower and see how well it works.

I want to use two of the Zmod Scope 1410-105 ADCs on an ECLYPSE Z7 board, but my application needs sample rates that are relatively low (5 to 10 MSPS). The data sheet for the AD9648-105 ADC on the 1410-105 board lists the maximum sample rate as 105 MSPS, and the minimum as 20 MSPS with the DCS on / 10 MSPS with the DCS off. The data sheet shows a typical, but not guaranteed, minimum sample rate as low as 5 MSPS. Is there any problem programming the 1410-105 boards though the Z7 board to give 10 MSPS or less as the sample clock input rate?