Ana
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Thanks for your reply. I don't know why the Zynq based design showed up in my question. Sorry about that.
Few questions-
- The addon board has a pin configuration for SCLK, SDA, VCC and GND. These don't match with my connectors. Do I make a cable in between to accommodate that?
- The 12 pin PMOD connectors on my board go to various pins on the FPGA. They do not go to SCLK or SDA on the board. Can I just designate the pins as SDA/SCLK?
- Currently I use the PMOD connectors just as GPIOs. I connected the various I/O signals in my block diagram to pins on JA, JB, JC, JD. That is not going to work now if I were to connect this I/O expander. I didn't invoke a PMOD IP to realize my design. Do I have to do so now?
- I know I will need to write the i2c protocol/communication part in .VHD, but I am not sure how to access the various I/Os after that.
Thanks
Ana
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Hello
I am new to the forum as well as to Digilent boards. I currently have a genesys2 dev kit. I am talking to it over ethernet and using the 4 PMOD GPIOs that come with it. I have to read in more inputs( outputs in future) and hence was wondering what is the best way to approach it. I came across the PMOD IOX add on. 1st question- would that work with my board? second, it looks like this addon board can talk to the digilent board via i2c. To use this add-on, on the vivado side, do I need to drop an AXI_iic IP and go from there? Are there any sample/demo codes that I can use to get started?
Thanks!
PMOD IOX add-on access via I2C
in Add-on Boards
Posted
Hi
Thanks for the detailed answers.
Pt 1 and 2 are well taken. Can I use an AXI IIC IP core to realize this setup? I was thinking in the lines of having an AXI_IIC IP connected to my microblaze. The IIC port on the IP is connected to SCL and SDA in the constraint file. I chose the board interface as custom. I am not sure if I am constraining it correctly. Output port is IIC, so should constraints be....get_ports{ IIC_scl_t} etc or what I have below should be fine as the correct pin assignment is what matters.
set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports {IIC_0_SCL_IO}];#IO_L12P_T1_MRCC_14 Sch=ja_p[2]//SCL
set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports {IIC_0_SDA_IO}];#IO_L12N_T1_MRCC_14 Sch=ja_n[2]//SDA
Now after generating bitstream, in Vitis, I can specify the IIC address - AXI IIC ( from xparameters.h file) and io_expander address ( my expander io address). Once that is established I can send and receive data on the data line and based on the AXI IIC IP register space I can check the TX_FIFO and RX_FIFO for sent and received data.
Will this method work or am I missing something?
Attached is my block diagram with AXI_iic
.