A.O

Thanks @JColvin, This is very helpful and I appreciate the help.

Thanks @JColvin, I was able to boot up via the SD card using your project file and it functions as expected. In my original project, I had only included the Zync processing block with a simple RTL module, but did not include the axi peripheral block. Can you confirm that this block is necessary in order to have the block diagram interface with the processor?

I am using a Cora Z7-10 board and have a sandbox project (Verilog) that can boot using an external SD card without issue. When I launch Vitis and import any UART example into my project, I can run that via JTAG and see that all of the examples work fine. I then create a boot.bin, that includes the fsbl, the bitstream, and the example.elf files - the FPGA does not boot properly. I can see that the Verilog circuit is working, but the UART example isn't. I am powering the board via USB, and I have confirmed that the baud rate and COM port is correct when running the examples using JTAG. I've attached the boot image and the bif file. Any help would be much appreciated. Boot_and_bif.zip