FPGAlearner

Thank you for this. I figured it out finally. I kept getting this after synthesis: WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. And I looked up a solution and had to type this into the TCL console: write_checkpoint synth.dcp

I have been trying all day to make a simple flip flop with the BASYS 3 and Vivado. This code below is correct. I have also used many other variations of this code, including Verilog instead of VHDL. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity first_flipflop is Port ( D : in STD_LOGIC; Clk : in STD_LOGIC; Q : out STD_LOGIC); end first_flipflop; architecture Behavioral of first_flipflop is begin process(Clk) begin if(rising_edge(Clk)) then Q <= D; end if; end process; end Behavioral; Constraint: #LED set_property PACKAGE_PIN V14 [get_ports Q] set_property IOSTANDARD LVCMOS33 [get_ports Q] #Button set_property PACKAGE_PIN W19 [get_ports D] set_property IOSTANDARD LVCMOS33 [get_ports D] #Clock set_property PACKAGE_PIN W5 [get_ports Clk] set_property IOSTANDARD LVCMOS12 [get_ports Clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform (0 5) [get_ports Clk] First, when I try to process the code it tells me that the clock cannot use LVCMOS33 even though when I watch people use this board for flip flops on YouTube they use the same clock W5 pin with LCVMOS33. So, to remove the error in the log I changed LVCMOS33 to LVCMOS12 or 18. Then, when I try to process the new code it tells me that the i/o ports do not work with the clock pin with the IBUF error. Not knowing any other possibility for this exact circuit I want to make, I use the following to bypass this error: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] Finally, everything should be working now right? No. Now, it tells me I do not have my Q and D constraints(even though I clearly do) and when I go into the i/o ports for Q and D it forces them on two random pins that I do not want them to be on(I want D to be a button/switch and Q to be an LED). When I try to change these pins it literally does not let me, every time I change the pin in the box it just puts the same pin they put back in. This is the error it gives concerning this: [DRC UCIO-1] Unconstrained Logical Port: 2 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: d, and q. At this point, I am exhausted and do not know if the circuit I want to build is even possible with my BASYS3. I just want to use a button/switch as D, the clock W5 pin as the clock, and an LED as a Q indicator. If anyone can help I would greatly appreciate it.