Hi Jkolvin,
Thanks for the reponse.
In preparation to sending you the files, I removed the body from all verilog files leaving just the module and port declaration.
To my surprise In that state I was able to read all the files in the normal way.
I therefore concluded it was something to do with the source? Can't think what at the moment, I will at some stage put things back one at a time.
The work around I had adopted was to open the project in the simulator, installed breakpoints in any files that did not have any then did a blind 'run all'.
Whenever a breakpoint was hit the simulator had to open that file.
Once a file was opened at least once, it's tab remained available for the entire session even when I come out of the simulator. Only had to do this process on first opening of the project.
The other work around was to use an external editor but one has to be mindful of the fact that Vivado is not the greatest at detecting that a file was modified externally and therefore requiring Vivado to reload it (it rarely does!), so to make sure I was using the most up-to-date file I had to Ctr+A, Ctrl+C in the external editor and Ctr+A, Ctr+V in Vivado's copy of the file.