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Kabs

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  1. Hi Jkolvin, Thanks for the reponse. In preparation to sending you the files, I removed the body from all verilog files leaving just the module and port declaration. To my surprise In that state I was able to read all the files in the normal way. I therefore concluded it was something to do with the source? Can't think what at the moment, I will at some stage put things back one at a time. The work around I had adopted was to open the project in the simulator, installed breakpoints in any files that did not have any then did a blind 'run all'. Whenever a breakpoint was hit the simulator had to open that file. Once a file was opened at least once, it's tab remained available for the entire session even when I come out of the simulator. Only had to do this process on first opening of the project. The other work around was to use an external editor but one has to be mindful of the fact that Vivado is not the greatest at detecting that a file was modified externally and therefore requiring Vivado to reload it (it rarely does!), so to make sure I was using the most up-to-date file I had to Ctr+A, Ctrl+C in the external editor and Ctr+A, Ctr+V in Vivado's copy of the file.
  2. Thanks JColvin, Actually I had done another major step which I forgot to mention. I created a brand new project, 'added' the same files again, but the result was the same. Does that then point to my Vivado install? On a side note, Anyboby knows if it is possible to develope for Nexys A7 via any other tool other than Vivado such as Quartus?
  3. Hi all, Have this project with a top level file and other non top level file all of which are included in the project hierarchy. The non-top level files are listed in the project hierarchy beneath the top level module file Everything has been working fine in that which ever file I click at (top level or otherwise) opens a tab for the file, as it should. Right now the only source file that can be opened is the top level file, clicking any of the other level files does nothing i.e. exactly nothing happens...the clicked file does not open. The file are visible in file explore in the same directory as the top level file. in the hierarchy below only ns.v can be opened, SSD.v and myUart.v cannot be opened Can someone please point me to what might be going wrong?
  4. Hi JColvin, Thanks for the response. Unfortunately there is absolute disagreement between assignments on my board and XDC/circuit diagram versions. By trial and error I have managed to place most of the pins for JA & JB as you see below paired with what the XDC/circuit says. In cases where I haven't (yet) found verifiable values I have put a question mark. I have fully verified the ones I have marked. I wonder, do I have a counterfeited board?, Are there such things?
  5. Hi All, I am fairly new to FPGA (but not hardware), coming from a mainly software background. I am developing within Vivado. I am having problems identifying the correct pins for Pmod connectors on my Nexys A7. There are differences between the circuit diagram and the .XDC file for the board. I am wondering which of the two to go by because I do not want to accidentally assign output to a pin which may cause problems if it was not meant to be assigned to. So far I have seen differences within JA and JB. most discrepancies are with JB JB XDC & circuit diagram assignments. XDC Circuit FPGA pin B3 B4 H14 B4 B7 E16 B5 B8 F13 B6 B9 G13 B7 B3 G16 I would be grateful if someone knows which one to go for (now and the future). Many thanks, Stephen.
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