Leonlin666

Hi, Kindly for you help to give your concerning as well as possible. Now we want to do dual mipi cam(pcam-5c) base on currently zybo-z7 platform, So can we make the external convert b'd according to existing of pmod ports? If can that how to define the pin of assignment for new MIPI2? And any potential issue need to note? Best Regards, Leon

Hi, In additional, Did you test whether the pin of MIPI_clk+- has normal waveform output during operation? Best Regards, Leon

Hi, Very thanks response as quickly! We have used 2017.4 and 2019.1 Vivado for this project. Just now we download the project of 2021.1 Vivado version and checked that all of code which both are kept same than before versions(Eg. XDC PIN of constrain, bolck design) as below pic. Now we want to do dual mipi cam(pcam-5c) base on currently zybo-z7 platform, So can we make the external convert b'd according to existing of pmod ports? If can that how to define the pin of assignment for new MIPI2? I think it shoule be related as my prevoius question. #MIPI1 currently set_property PACKAGE_PIN G20 [get_ports {cam_gpio_tri_io[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {cam_gpio_tri_io[0]}] set_property PULLUP true [get_ports {cam_gpio_tri_io[0]}] set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS33} [get_ports cam_iic_scl_io] set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports cam_iic_sda_io] set_property INTERNAL_VREF 0.6 [get_iobanks 35] set_property -dict {PACKAGE_PIN J19 IOSTANDARD HSUL_12} [get_ports dphy_clk_lp_n] set_property -dict {PACKAGE_PIN H20 IOSTANDARD HSUL_12} [get_ports dphy_clk_lp_p] set_property -dict {PACKAGE_PIN M18 IOSTANDARD HSUL_12} [get_ports {dphy_data_lp_n[0]}] set_property -dict {PACKAGE_PIN L19 IOSTANDARD HSUL_12} [get_ports {dphy_data_lp_p[0]}] set_property -dict {PACKAGE_PIN L20 IOSTANDARD HSUL_12} [get_ports {dphy_data_lp_n[1]}] set_property -dict {PACKAGE_PIN J20 IOSTANDARD HSUL_12} [get_ports {dphy_data_lp_p[1]}] set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVDS_25} [get_ports dphy_hs_clock_clk_n] set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25} [get_ports dphy_hs_clock_clk_p] set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports {dphy_data_hs_n[0]}] set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports {dphy_data_hs_p[0]}] set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports {dphy_data_hs_n[1]}] set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVDS_25} [get_ports {dphy_data_hs_p[1]}] I'm looking forward to hearing from you, Best Regards, Leon

Hello, I'm using a Zybo Z7-20 board together with the Pcam 5C camera module and I have a question regarding the MIPI D-PHY settings in the Zybo-Z7-20-pcam-5c project. We can't get the normal picture just only see the abnormal picture as below. 1>. We use an oscilloscope to see the hs_data0/1+- waveform, But can't see any waveform from hs_clk+-. 2>. After check the schematic and vivado of constrans that LP port which are not used the differential pairs. 3>. The mipi port of bank35 isn't used 1V8 vooc. 4>. if we want to use dual pcam-5c for Zybo Z7-20 board for dual 1080p mipi cam, Do you have any advice of PIN XDC constrans assignment configures? What are the settings for the MIPI D-PHY to decode the 2-lane MIPI signal received from the PCAM 5c camera board? Kindly for you help to clarify the relation items in order to fix the issue。 I'm looking forward to hearing from you, Best Regards, Leon