Anthocyanina

I only have an AD2, and my experience with it, and the support on the forum (including your team listening to user suggestions, which I don't know of any other company that does this, much less as fast as it's been here), has been absolutely amazing, and that has led me to consider Digilent's products for the future, but there are a few things which make the pro series hard to justify, so i'll comment about the last 2 questions
What sampling rate and analog bandwidth do you typically need for your current and future measurements? (Open Text)
The bandwidth of the pro series currently offered is really ok, the sampling rate however could be higher. for a 14 bit oscilloscope, of course faster AD converters would of course be significantly more expensive, but a 200MSPS sampling rate would be a good match for the 55MHz bandwidth.
What features or improvements would you like to see in future products? (Open Text) 
A big thing would be more voltage ranges than the current two. It being 14 bit makes it liveable, but it would be a really good improvement if more ranges were added, and in that form factor, I would think it wouldn't be impossible to accomplish.
I don't know about the acquisition rate of the pro series, but the AD2 seems to be about a few dozen waveforms per second. If the pro series is in that ballpark, it would also be a very welcome improvement if it could do at least a few hundred waveforms per second, and perhaps if this was accompanied with intensity graded display, it would make for some nice qol improvements, as it would allow us to find rare events more quickly and without having to resort to the persistence view. This, again, from having no experience with the pro series, so I don't know if it already works this way, but from video reviews i've seen, it doesn't.
Buffer size, while 16k points in the AD2 are still useful, and so 32k in the pro series would as well, having at leat 1M points for repeated acquisition would be really good as it would allow for a faster sample rate at slower time bases, and some times that is really important. I use my AD2 for most of what i do, but there are cases in which i have to use one of my bench scopes because of the buffer size(or when i need more bandwidth), so having one of Digilent's instruments with a larger amount of memory, with how incredibly good the waveforms software is, it would, at least in my case, result in me pretty much never again needing my bench scopes.
Input impedance would also be a nice qol improvement, if it had a switchable 50 ohm/1Meg input impedance, but this isn't super critical, at least for my uses, just something that would be really nice to have, and i think would make sense under the "pro" label :)

there is a connection diagram  this shows how to connect it, 1+ and 2+ are the scope channels, w1 is the generator output, and you see 1-, 2- (the negative of the scope channels) and ground are tied together

i'm so blind! i skipped over that setting each time i was trying to figure this out. that works perfectly, thank you!

Hi @Anthocyanina
Use the Offset of AM

Thanks, that looks so cool now! 😄
 

Desktop 2023.03.17 - 17.19.52.04.mp4    

Hi @Anthocyanina
All the installers are on aws server so the download speed should be the same. The difference may be in your OSs.

Hi @Anthocyanina,
I'm not certain why this might be; I just attempted to redownload WaveForms on both Chrome and Firefox on my Windows 10 machine and was able to successfully download both the formal release and the 3.19.27 beta in about 10 seconds each (~6.0 MB/s download based on what the Firefox on-going downloads told me).
I know that there was recently a browser cookie update to some of the Digilent websites and that some parts of the website would run very slow or not at all if you blocked different cookies, but my understanding was that issue got resolved a couple of weeks ago. But even if this was the issue, I don't know why it would only affect your Windows system but not the Linux system. I will ask some my coworkers to see if this can be replicated.
Thanks,
JColvin

Hi @Anthocyanina

Hi @Anthocyanina

 

Hi @Anthocyanina
The next version will bring such options:

you can do it like this with a math channel

Hi @Anthocyanina
Wow, it looks awesome 😃
Indefinitely and it is reset with Run/Single

@attila Thank you! I had not noticed that menu, is there a setting to tell it how much time to keep in the display? or does it infinitely accumulate the points and display them? thanks again, it works quite nicely :)

@attila Thank you! I had not noticed that menu, is there a setting to tell it how much time to keep in the display? or does it infinitely accumulate the points and display them? thanks again, it works quite nicely :)

Hi @Anthocyanina
Yes, see the following:

That's the noise band, you can disable it by unticking the noise box in the channel settings. It is useful to have it on as it will show there can be some higher frequency content there

Hi @Anthocyanina
Unfortunately such option won't be available with AD2 since the device FPGA is already fully utilized, eventually for other/newer devices.
Thank you for your post.

Hi @Anthocyanina
Yes. It depends on the noise. What you are seeing is the derivative +/- sample to sample noise it captures. In M1 I didn't multiply it with the rate so you can see a +/-~2mV noise.
You probably want if(isNaN(prev)) prev = C1; and having the initializer code var prev = NaN;  for the first sample to be zero.

Hi @Anthocyanina,
Yes, the 3D stp file is available in the Additional Resources at the bottom of the Basys 3 Resource Center; https://digilent.com/reference/programmable-logic/basys-3/start#additional_resources. Any 3D model for our products, if they exist, will be in a similar location in their own Resource Center.
Digilent does not partner with any other website for creating or specifically hosting our 3D models (to the best of my knowledge anyways).
Thanks,
JColvin

Thank you @artvvb! being completely new to FPGA it took me a while to figure out how to do it, so I'll leave it here in case anyone else ever wonders about this while following the tutorial for the first time.
module blink( input clk, output led, output reg [3:0] an //added the anodes as outputs ); reg [24:0] count = 0; assign led = count[24]; assign an =4'b1111; //assigned the anode outputs as high always @ (posedge(clk)) count <= count + 1; endmodule  

Hi @Anthocyanina,
From the FPGA's perspective, the seven segment anodes and cathodes are active low. By default, when the FPGA is configured, Vivado applies a weak pulldown to each of the unused I/O pins - pulling the outputs to ground while allowing an external pullup resistor to override it if necessary. It might have been possible when designing the board to avoid the 7seg illuminating in this situation by including pullup resistors on the nets connecting the FPGA pins to the display, but these were not included.
Before programming the bitstream into the board, the IO pins are left floating - no pull up or down - so there's no path to push current through the display.
The default after configuration can be changed, either by including ports for the anodes or cathodes and pulling them high, or by setting the default pull for unused pins to either pullup or pullnone (which could make other stuff happen, like illuminating unused LEDs, since doing so affects everything). See here for more info: https://support.xilinx.com/s/question/0D52E00006hpZVASA2/what-is-the-pin-state-if-i-didnt-use-them?language=en_US
Thanks,
Arthur
 

Hi @Anthocyanina,
I personally deleted the versal folder that was in the file location that I referenced; I haven't personally experienced any detriment in my Vivado experience (depending on what devices you have installed, you might see some sort of Warning that Vivado can't find the parts for Versal devices), but maybe your experience will be different. There's always the backup option of uninstalling and then reinstalling Vivado if something goes wrong.
This goes outside the scope of the Digilent Forum at large and is purely JColvin's recommendation (not Digilent endorsed or anything like that) but I've personally used an application call WinDirStat, https://windirstat.net/, to analyze and find where and how my hard drive/SSD space is being taken up by different files.
Thanks,
JColvin

Hi @Anthocyanina,
That seems to be the correct board selection based on the Xilinx Board Store (it seems to be file version 1.1 rather than version 1.2 like Digilent has on our own board files which we supplied to Xilinx (https://github.com/Digilent/vivado-boards/tree/master/new/board_files/basys3/C.0), but regardless that shouldn't have brought up this warning, though you should be able to safely proceed with the HDL projects in the meantime.
I don't think leaving out Vitis should cause this issue, at least that I am aware of.
I know there are some files within the Xilinx installation that can be safely deleted to save you more space on your hard drive since that is a concern for you; the place I would be looking in the:
folder since a lot of Versal parts get installed in there (even if the box during installation is left unchecked) which are quite large. I safely deleted those parts from the installation as well as other parts that I do not intend to use from the Xilinx:/Vivado/2020.1data/parts/xilinx/ folder for various artix7, kintex7, virtext7, zynq, etc parts that I know I do not need. But the biggest culprit was for sure the Versal parts and the zynquplus folder that saved me several gigabytes of space (and the multiple copies of the multi gigabyte identical EULA that is included in various parts of the file structure).
Thanks,
JColvin

Thank you all for your replies, I realised I had not uncommented the first get_ports clk line in the xdc file and now it generates the bitstream!  
About the board being installed warning, when i create a new project, this is what i see when selecting the board, is this correct?
I didn't install vitis since i didn't have enough space and only plan to do hardware designs for now, does this have anything to do with the warning?

Thank you!

Take a look at the errors it gives you at the bottom tab of the interface. This should have the reasons why the bitstream generation failed.
 
It looks like you didn't assign non-default pins in your project. Even if the "default" setting is the one you want, you need to manually assign the pin I/O Standard in the xdc file, or in the pin planner.
 
~Kvass