[Need help with setting the FFT IP correctly]

I am trying to accomplish a simple FFT exercise using the LogiCORE FFT IP v9.1. I generated a 10MHz singletone sinusoid using LogiCORE DDS compiler IP v6.0 and feed it to the FFT IP. After calculating the absolute value of the output from the FFT, I get multiple frequencies as the FFT output. What I am doing wrong. Following is the simulation output. You can see the FFT_out has multiple peaks.

Following is the block diagram I am using for this exercise:

Let me explain the block diagram in detail:

• sys_diff_clock is 50MHz and clk_wiz_0 is producing a 100MHz clk_out1.
• dds_compiler_0 is set up as follows to generate a 9.9990844726562500000 MHz sinusoid:
• xfft_0 is set up as follows:
  
• xlconcat_0 produces a 32bit output by concatenating 16bit output from dds_compiler_0 as real and 16bit zeros from xlconstant_0 as imaginary part.
• m_axis_data_tdata from xfft_0 is sliced into [15:0] and [31:16] as imaginary and real parts, respectively, and squared using mult_gen and added together using c_addsub_0 to form the absolute values.
• Both mult_gen_x and c_addsub_0 uses signed operations. Finally, the output is FFT_out which should show a single peak.
• In the simulation, I am showing everything as signed magnitude radix.
• I am using Vivado 2020.2.

My question is why I am not seeing a single peak. Any help will be appreciated.