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longcntn96

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Posts posted by longcntn96

  1. On 5/26/2022 at 9:04 PM, zygot said:

    No, I'm saying that I believe that the use of BOARD_PART_PIN, which is applied to all IO identifiers as a place holder that references a different source file, is associated with only the latest versions of Vivado. I'm wondering how you even have a reference to BOARD_PART_PIN in your constraints file. If you use the constraints from Digilent you won't see it anywhere. I've never seen this with the tool versions that you are suing; and I still do use VIvado 2019.1 frequently. There must be something about the way that your project was constructed; perhaps a tcl script writtne for a later version of VIvado?

     

    Actually i didn't get the BOARD_PART_PIN warning when i used the  pmodOLEDrgb IP.  It would be helpful if someone can confirm that the DHB1 IP works fine

  2. Hi,

     

    I am trying to work with the DHB1 pmod module by using Pmod IP following the instruction Getting Started with Digilent Pmod IPs.

    I tried with vivado 2019.1(using library of v2019.1) and 2018.3(using library of v2018.2) and always got the same warning when running synthesis:error.PNG.91e516b7001c3b9c256c0c8e235722c8.PNG

    The XDC file in synthesis design:

    XDC.PNG.ec99f7460440b5d9444b88c463840692.PNG

    I ignored this message and continued creating a sdk project and then ran the example program, but no signal is made to the pmod pin.

    This is my block design:1587462607_blockdesign.thumb.PNG.d6c941186fe3b021eed553af4e6b9148.PNG

     

    Can someone tell me what did I miss? and how to fix it?

    or If you can try to run synthesis with another vivado version(e.g. 2018.2) and let me know if you get the same message or not

     

    Thank you!

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