I don't think that you understood my first answer. In the case where the PS controls the external DDR memory ( all of the Z7000 boards sold by any vendor that I'm aware of ) the MIG IP is completely irrelevant; you can't use it. The MIG IP is for external memory interfaces connected to logic pins ( as for the Arty A7 board ). The only way for the PL to get access to the PS DDR is through one of the master or slave AXI busses. There are a number of Xilinx AXI IP that might be usable, though the best way would be to write own AXI master or AXI slave interface; this is not for the inexperienced FPGA developer ). The AXI streaming IP can DMA data between PS external memory and the PL. You will still need to have some understanding of how AXI works.
There's always the limited, but still potentially alternatives, like using Xilinx AXI BRAM controllers in a configuration that allows access to DPRAM to both the AXI IP and your own PL code. This is conceptually the easiest method but requires PS software to either copy data to PS memory or use the ZYNQ DMA controller to do it.
As I mentioned the only ZYNQ FPGA board that I know of with PL connected external memory is the ZCU106. In this case, UltraScale+ external memory controller IP is not the same as Series7 MIG IP.
The DDR in ZYNQ based boards are controlled by the PS so you can't control it from the PL. You can use an AXI master to transfer data between the PL and PS DDR however. There aren't a lot of Xilinx boards with external DDR connected to the PL.The ZCU106 is the only one that I'm aware of.
