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vcb1

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Posts posted by vcb1

  1. Hi @BogdanVanca

    With the compiled option is working, now it compiles with no error and i see the color bar in the screen. Regarding the demo now i have a problem with pass-trough mode "gt tx and rx are not coupled/bonded". I guess this is a matter of the input source used, I will investigate this, in any case my main issue was to compile and be able to run the demo

    By the way, as you said at the end of the guide " you simply have to give a path for the fsbl file, and deploy the project on your board."  i just followed the same instrunction as in the hello world example to import the file ..\Genesys-ZU\sw\ws\5ev_fsbl\Release\5ev_fsbl.elf

    image.thumb.png.d7c650b6222908285aab8a4bbcb44b2a.png

    Just tin case is useful to include this in the guide for the next one.

    Regarding the Vivado part to see the hardware, how do i get the .xrp file? should i use the same as in the release (https://github.com/Digilent/Genesys-ZU/releases/tag/5EV/HDMI/2020.1-2?_ga=2.2040497.1606460636.1650351435-317001971.1647265744)? 

    I did not try the other option (import from release) in case i test in the future i let you now.

    Many thanks for your help!

  2. Hi,

    I am working with the demo for the genesys zu board (https://github.com/Digilent/Genesys-ZU/tree/5ev/oob/master?_ga=2.30403711.1708251486.1649661649-317001971.1647265744) and i have an error to display a pattern in a monitor.

    I am wondering if it is just a matter of the type of display port connector. In other words if i need an active mini display port.

    I am trying the DP-bist command to test the displayport but i get this error.

    root@GenesysZU:~# DP-bist
    failed to find mode "1920x1080" for connector 42
    failed to create dumb buffer: Invalid argument

    When i test with modtest, looks like the display port is disconected.

    root@GenesysZU:~# modetest  -   -M     -M xlnx
    Encoders:
    id    crtc    type    possible crtcs    possible clones    
    41    0    TMDS    0x00000001    0x00000000
    
    Connectors:
    id    encoder    status        name        size (mm)    modes    encoders
    42    0    disconnected    DP-1               0x0        0    41
      props:
        1 EDID:
            flags: immutable blob
            blobs:
    
            value:
        2 DPMS:
            flags: enum
            enums: On=0 Standby=1 Suspend=2 Off=3
            value: 3
        5 link-status:
            flags: enum
            enums: Good=0 Bad=1
            value: 0
        6 non-desktop:
            flags: immutable range
            values: 0 1
            value: 0
        4 TILE:
            flags: immutable blob
            blobs:
    
            value:
        20 CRTC_ID:
            flags: object
            value: 0
        43 sync:
            flags: range
            values: 0 1
            value: 0
        44 bpc:
            flags: enum
            enums: 6BPC=6 8BPC=8 10BPC=10 12BPC=12
            value: 8
    

     

    In the readme i see that there is no information regarding the type of display port: "To successfully run the Display Port test, an Display port capable monitor is required, as well as one Display Port cable"

    Is it possible that i need an active display port?

    Thanks,

     

     

     

     

  3. Hi @BogdanVanca

    Thanks for the suggestions. I have tested the hello world and works perfectly. I have been trying to replicate the issues on this guide with the example of the hello world and I solved some issues until that error in the make file. I am beginner on this topic so any help is always welcome.

    I guess you mean to clone the HDMI project from here https://github.com/Digilent/Genesys-ZU/tree/5ev/demo/hdmi or? I will do that and let you know.

    And yes please, let me know if you find something new. Of course as i am also replicating the guide i can help you to update the steps and test any new process for this "how-to" guide.

    Many thanks

     

  4. 17 hours ago, thinkthinkthink said:

    Also you need a post-implementation bitstream for the project to work on the board. So show us the Message tab and the Implementation log to see why vivado couldn't implement your design. The Synthesis log you uploaded wasn't enough.

    Sorry there was a mistake from my side.  i've realized i had an error renaming the buttons of the Genesys-ZU-5EV-D-Master.xdc file. Now i can generate the bitstream as explained in the guide. Tehrefore the part of the vivado is ok.

    However i repeat the process in the vitis part and i get the same error.  I am not sure if the part of the "Change the BTN_MASK and LED_MASK macros" i did it correct. should i add the number in binary format? i mean i have tried:

    image.png.e8d5b2d89aac7ed2674a9dab9d954e8b.png

    but i sitll have an error

    image.png.0d17dfcef12f06f50ab22ce0308ec5f5.png

     

    and here the log of the xsct console

    xsct_console_log.txt

    I include also the xparameter.h file where the GPIO are defined xparamters.txt

    162914031-ef87a999-e4e7-4d1e-9dd3-7f9201

     

    Many thanks for your help!

     

     

  5. 7 minutes ago, thinkthinkthink said:

    You should follow this Genesys-ZU Hello World Demo Project Guide to get a better idea on how to work with our Genesys-ZU variants before trying anything else.

    Yes, i did already the Hello world demo and it works fine. 

    Now i am trying to follow the https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi.

     

     

  6. Hi,

    I have recently bought the Genesys Zu 5EV and i have some problems with the tutorial "Getting Started with Vivado and Vitis for Baremetal Software Projects" https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

    i have tried to reproduce all point step by step but i have some errors and i am wondering if there is some problem on the guide or with the versions. Here are all steps i have followed and the problems/errors i get:

    Vivado part

    In the step "Add a Zynq UltraScale+ Processor to a Block Design"

    In the part that says "The needs of your project may require that you change some of the default settings of the PS. To edit its settings, double click on it to open the configuration wizard." When they suggest to add a second clock, looks like it is not necessary, if I add it then I have an error afterwards about where to connect this pin.

    To solve this issue I have removed this clock (i assume is not necessary to have a second clock here). Tehrefore i have also avoid the part of "add a Concat IP to your block design, and manually connect it to the pl_ps_irq0 port."

    In step "Add GPIO Peripherals to a Block Design" part of  AXI_GPIO_BUTTONS

    First i add the xdc file Genesys-ZU-5EV-D-Master.xdc for the contraints

    In the guide it says "_the button interface to “btn_tri_io[#]”, where # is a decimal number, counting up from zero. When finished, save the file_.". However the button on the Genesys-ZU-5EV-D-Master.xdc starts on 2 until 6

    162710557-71bd74d0-ce5f-4bdc-86e0-5dd922

    I have re-named the file as suggested in the guide
    162760592-b563c725-1c13-4518-9962-88cded

    However the guide says "In particular, the width of the GPIO interface must match the number of buttons available on the board." and i f i am not wrong in the genesys zu board there are 7 buttons not 5 (BTN0, BTN1, BTNL, BTNR, BTNU, BTND,BTNC) but the xdc file only defines 5, is this correct?
     

    In step Edit the Address Map


     Here the values are different that the ones of the guide, but i have checked that there is no Assigning an segment to address 0 to avoid errors as explained in the guide. is this correct?

    162753946-0e370e09-10a2-40eb-b732-af942f


    In step "Validate a Block Design"

    it shows an error in the pin saxihpc0_fdp_aclk

    162713721-454fe05e-5dd5-4cfd-b00f-363534

    162713805-3e4ba247-ef41-49dc-b830-e19e29

    Following the figures of the guide (even if they are not the same for the zynq ultrascate), I have connected the pin that produce the error (_saxishpc0_fdp_aclk_) to the pin _pl_clk0_ (clock) pin. Sfter that the validation is ok, is this correct?

    162714797-dcdfad9e-6fa2-4687-aeca-1058be

    The validation now is ok, but it shows the following warning messages

    162715327-39a735ed-92a3-4b4d-bced-584a95

     

     

    Vitis part

    In the "Create a New Application Project"

    When i have to select the Aplication project details. Which Processor should i use? In the guide the picture is different. Is it correct to use the first one _psu_cortexa53_0_ ?

    162726956-6a3ebdf4-7e12-4b7b-aebc-e6b06b

    162908882-18fa9d46-9012-4691-a372-0d9854

    As suggested in the guide " Change the BTN_MASK and LED_MASK macros so that they contain a number of '1's equal to the number of buttons and leds connected to the GPIO peripherals in the hardware design." Here i assume is 5 for buttons and 4 for leds as i did it in the vivado part is this correct? how do i know the buttons and leds connected to the GPIO peripherals in the hardware design ?

    162730891-97fd3a4a-be69-496c-bd38-acb1bc

     

    In the step "Launch a Vitis Baremetal Software Application"

    When i try to make  _Run as → 1 Launch on Hardware (Single Application Debug)._ It pops up an error window.

    162731989-841a61e4-d2df-494b-b415-18037e

     

    162729183-92738430-f7e8-4b3d-a315-942c85

     

    162730076-04f63181-6269-48ad-bb56-8932a6

    If i run with the option " Launch on emulator" looks like is working, but i do not knw how to test the buttons and leds there.

    162732927-05412972-4a90-40f1-bade-dd3a29

    Many thanks,

     

    log_build_vivado_project.txt

  7. Hi,

    I am trying to follow the HDMI for the Genesys ZU-5EV board as described here:

    https://digilent.com/reference/programmable-logic/genesys-zu/demos/hdmi?redirect=1

    I have and error in the "Launch the Vitis Baremetal Software Application" 

    image.png

    It looks like a path problem with the "/" and "\", which i guess is also related with the makefiles that the demos is using in 5ev_boot and 5ev_hdmi_demo_system. There is one line which clearly is not in my computer:

    XPFM_PATH = C:/Users/bvanca/Downloads/Zybo-Z7-20-HDMI-2020.1-1/hw/Genesys-ZU/sw/ws/5ev_hw_pf/export/5ev_hw_pf/5ev_hw_pf.xpfm

    I have tried to change this path, but i did not fine this file in the folder of the demo.

    I have also changed the path of the lscript.ld as i realize that was also wrong and after clean and build again i still have error, but this time there is almost no information. It seems that there is still an error in the make file

    image.png.492a18b26b6c6526fea0988a1d5a897f.png

    After that i have tried to run the application and i get the following messages in the Tera

    image.png.6a4cac7469713292a3b66569b42db44d.png

    Any idea on how to change the make files? should it work directly in the  Genesys ZU-5EV board? 

    Many thanks in advance

    Victor

  8. 1 hour ago, elodg said:

    Correction: FMC Pcam Adapter offers limited compatibility on ZU+, like the Genesys ZU. At least one camera out of four can always be mapped to any pin-out. Full info here: https://digilent.com/reference/add-ons/fmc-pcam-adapter/reference-manual?redirect=1#fpga_io_architecture_compatibility.

    Yes, this is in addition to the two MIPI ports on-board.

    Good news then. This will allow us to have 3 cameras simultaneously.

    Thanks!

  9. 10 minutes ago, thinkthinkthink said:

    The FMC Pcam Adapter is not compatible with any UltraScale+ FPGAs, so any board that has such an FPGA not just the Genesys-ZU variants.

    And yes, any MIPI camera should work. 

     thanks for the fast answer.

    Is there another similar adpater to work with more than 2 cameras in the Genesys ZU board?

    On the other hand, i asume that i can work at least with the two MIPI interfaces in the Genesys ZU board.

     

  10. Hi,

    First of all sorry if this question is not in the right forum.

    I am paning to by the Genesys ZU: Zynq Ultrascale+ MPSoC Development Board in order to prototype an image processing system, which will contain several cameras (at least 2 but potentially more).

    I see that the board has 2 Mipi connections which assume allows to connect 2 cameras like this ones (https://digilent.com/shop/pcam-5c-5-mp-fixed-focus-color-camera-module/).

    Is it possible to use another cameras as soon as they have mipi conection?

    Moreover i see that there is an apter (FMC Pcam Adapter) to connect up to 4 cameras. However the web page says: "The FMC Pcam Adapter is compatible with Digilent's ZedBoard, Nexys Video, Genesys 2, and NetFPGA-1G-CML". Means this that is not compatible with the Genesys ZU? Is there a way to have such a connector for the Genesys ZU?

    Many thanks in advance!

    Victor

     

     

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