RemyBlt

Hi, quick update for those who might have this problem later. I've managed to solve this issue (well, generate a bitstream, not sure if it really works yet) by checking in the digilent boards folder from here. In the "Nexys4 DDR" folder there is a file named "part0_pins.xml". In this you will find what is used to generate the .xdc file from the Block Design for the SD slot. <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/> And from this you write lines in this format in a constraint file that you can create if needed to tell to your wrapper which pin you assign to which pin of the FPGA. set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports sd_pin1_io] And in the Block Design, double click the PModSD block and set the "Board Parameter" to "Custom" to tell the software that you don't want it to generate an automated constraint file for this block. I've not yet tried to do a software test to be sure that this trick indeed solved my issue since I've some other issues with petalinux and the SD card (obvious incompatible drivers from the PModSD drivers) but that might be a hint for your own work.

Maybe it's a dumb answer but I've done the mistake once when trying to make zsh work resulting in the same kind of error. Is you default terminal bash ? Because even though you run bash when building petalinux, some script will be launched with the default terminal selected. To check this, run this command. echo "$SHELL" If the result is not /bin/bash Then you know that you have to change it. If it's not the problem, double check the UG1144 page 9 to 10 to see if you have installed all the necessary libraries

Hi, I'm currently new at the FPGA development field. I'm trying to implement Linux on a SD Card on a Nexys 4 DDR using petalinux and the useful automation tools with the Block Design in Vivado 2020.2. The problem that I'm facing is that when I try to add the Onboard Micro SD Slot to the design, it uses the IP made by Digilent named PmodSD_v1_0 made for the Arty board. And when I try to generate the bitstream, it fails with these messages : I've also tried to use the answer from this forum made by @jpeyron found here but the IP made for the Nexys 4DDR is for Vivado 2018.3 and he gave the project without the IP source so I can't generate the block with his parameters for my own project. Here is the design that I have made : I've also tried to re-generate the IP block from the git with my board as a parameter but it fails to find the correct pins : I have also tried to find in the elaborated design where all the pins are connected to manually assign all the pins but some of them are not connected because of these errors so I can't be sure about which pin I've to connect to which part of the SD slot. Does anyone could help me to find a solution for this problem ? Thank you for reading, RemyBlt