BMC99
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Posts posted by BMC99
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Hello,
Trying to run the PCAM 5C demo. I only have access to the Z7-10 board with the XC7Z010 part but the project available for download targets the XC7Z020 part.
Seems to me like it should be able to run on either board. I opened the vivado project and changed the settings to target the z7-10 board. I updated all the IPs as automatically prompted to do so in vivado, regenerate the bit file, export the new hardware with bitstream file, open SDK, target the new hardware specification, regenerate the bsp and rebuild the project. No actual architecture changes in vivado or code changes in SDK. I'm using the pcam_vdma_hdmi bsp and project. I connect all the hardware to the board (pcam and hdmi monitor to the tx port). I launch the debugger and step past the initial breakpoint at init_platform. Nothing happens. The menu doesn't appear in my com program (tera term) and no video out.
After adding a few breakpoints where it looks like things are falling down is in the call to DDynClk_SetRate within the VideoOutput class, which runs at line 85 of main.cc. By stepping through with breakpoints it looks like all the other commands in this class appear to run OK, but it never gets beyond line 80 of VideoOutput.h. I don't think a result is getting returned to "Status". Might be tough to answer but what might be going on?
The video_dynclk block is still present in the design. Has it been compromised somehow by switching the target SoC device?
Thanks.
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Was pulled away from this task for a few days.
I'm using the P2 IIC.
Actually using the xilinx ZC702 board with the digilent FMC adaptor. That means the i2c traffic goes from the PS I2C port through an I2C mux PCA9548ARGER on the xilinx board to the FMC I2C port. The scope shot that I posted was taken right at the pins of the TCA9546A on the pcam adaptor, so I know the traffic is getting through that mux correctly.
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Sorry but why do you think that?
The data line is high for 3 consecutive rising edges from time about 120 us to 140 us, then low for 5 consecutive rising edges.
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Trying to enable each of the 4 output channels on the TCA9546A.
Sheet 14 appears to be the relevant section of the datasheet: https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftca9546a
My A2, A1 and A0 pins are all tied low in hardware.
Refer to the attached scope shot. Blue is data yellow is clock.
After the initial write, I write 11100000, which should corespond to the fixed slave address and the state of those 3 pins.
Then I write 00001111. The first 4 bits are don't cares and the 4 ones should enable all 4 channel outputs.
However, I still can't get anything out of any channel with any subsequent writes.
Is there another subsequent or prior write I have to do? What could I be missing?
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On 2/2/2022 at 7:20 AM, elodg said:
CSI-2 can carry different data types, but uncompressed video data rarely deviates from raster order in the industry. The PCAM 5C is configured for RAW10 format. Each pixel (bayer filtered) takes up 10 bits. Pixel are transmitted consecutively for a complete horizontal line. Horizontal lines are transmitted consecutively for a complete frame. The horizontal resolution is the number of pixels in a line. The vertical resolution is the number of lines in a frame. This is how the CSI-2 Receiver block gets data from the PCAM 5C and outputs on AXI-Stream all the same.
There can be exceptions for interlaced frames, compressed data like JPEG, or status information. None of these are in use in our demo.
OK thanks for the info.
If I can ask for one other clarification:
The CSI-2 receiver block outputs 4 pixels as a 40 bit std logic vector.
Like you said pixels are transmitted consecutively for a complete horizontal line from pixel 1 to say pixel 1920. So the first write would contain pixels 1 to 4.
Can I assume bits 39 to 36 are pixel 1 and bits 3 to 0 are pixel 4?
Thanks.
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Hello,
Looking to get a bit more clarity about the data stream coming out of the provided open-source MIPI CSI 2 Receiver block in the Zybo Z7 PCAM 5C vivado demo project.
The project indicates that the block outputs 4 10 bit pixels per stream.
How is the stream data from each frame organized?
Let's say I have a 1080p frame.
Will the block output pixels located at horizontal line 1, vertical lines 1-4 with the first stream, then horizontal line 1, vertical lines 5-8 with the second stream,
all the way to horizontal line 1, vertical lines 1917-1920 and then move to the second line and output horizontal line 2, vertical lines 1-4?
Or is it organized differently?
Thanks
Zybo Z7 Pcam 5C Demo - Run on Z7-10 instead of 20
in FPGA
Posted
Sorry just coming back to this now. Thank you for the link. I hadn't previously found that page with multiple releases for different vivado versions and the -20 or -10 versions of the board. I'll retry with the release appropriate for my setup.