rustem
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Posts posted by rustem
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On 5/1/2021 at 12:28 AM, tsarquis said:
create_generated_clock -name syzygy_c2p_clk_p -source [get_pins top/ZmodADC1410_Controller_0/U0/InstADC_ClkODDR/C] -divide_by 1 [get_ports syzygy_c2p_clk_p]
I get similar warning. How did you solve that.
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Eclypse Z7 and ZMOD-ADC1410 connection
in FPGA
Posted
I started the project before new controller released. Then let me try new one. I hope there won't be spikes
. By the way, do you get clear reading from ADC?