EngineerHW

We have implemented Xilinx Tri-Mode Ethernet IP in the Digilent GeneSys2 board. We have built our own wrapper with some of the Xilinx supplied example codes. We encounter some issues when running with the NI Labview: System: Windows 10, LabVIEW 2019. VISA Timeout is 2000ms. Devices are Digilent Genesys2 boards. Using Xilinx Tri Mode Ethernet IP. TCPIP0::169.254.20.20::7::SOCKET, and/or TCPIP0::169.254.20.30::7::SOCKET. Troubleshooting using a single Digilent Genesys2 board. • Devices will operate for minutes or hours, then will Timeout on Read. This leaves unread data in the Genesys2 buffer. The unread buffer data will offset all subsequent Read data. Board must be power cycled or Boot from Memory and close the Labview application and restart to recover. Sometimes after a Timeout, the Genesys2 will also fail to respond to ping. Process: VISA Open, Ethernet Loop() * Also, the Labview applications will fail to connect to the hardware. The only way to re-connect is by re-programming the FPGA and re-starting the LabView. It can run for minutes and then in the middle of the test it could loose connection after a few minutes. * On the earlier versions of WIN 10 STE (Windows 10 v 1809), the board can run for 10 hours without getting the timeout. The problem is exasperated with newer versions of Windows. The attached file is a depiction of how are test is being performed. Any thoughts or recommendations are greatly appreciated. Test_Scenario.docx

I was looking at the reference manual, specifically interested in the 5EV option. Is it accurate that this module only has 34 differential IO that can be used and assigned by the user? Thanks

Is there a pdf version of the reference manual for the Genesys ZU board. When I click on the link it takes me to the web version of the manual. Thanks

Is there a pdf version of the reference manual for the Genesys ZU board. When I click on the link it takes me to the web version of the manual. Thanks

Thanks. Yes, my question was indeed going at 10G over fiber cables using SFP connector.. I will look at the Genesys ZU for further detail.

Does the Genesys 2 Kintex-7 FPGA Development board support data transfer over fiber?