rehsd

...and with the LCD working:

I'm currently working on building a 16-bit processor (breadboard/PCB-based). As part of this, I'm using an Arty Z7 to prototype concepts, and I have a VHDL version of the processor running. I'm using the HDMI output of the Z7 as a debug screen, which has been great. A recent video giving a bit of an overview: I'm still working on the project. I'm posting updates to Building a 16-bit CPU on an Arty Z7-20.

@JColvin, thank you! That is helpful.

I was able to resolve this issue. For some reason, the block design wrapper was not updating with my changes. I deleted the wrapper, recreated it, and now everything seems to be working as expected.

RESOLVED. I had to delete the block design wrapper and recreate it. Using an Arty Z7-20, I am able to start a new project and add lines to the constraints file to get onboard LEDs to work in a simple test setup. I also have an existing project based on a Digilent demo project. In this project, the information I enter in the constraints file doesn't allow me access to the onboard LEDs. This project has a ZYNQ7 Processing System in the block design, connected to FIXED_IO. Does this pre-empt the information in the constraints file? As an example, the attached images show a simple test setup, which works fine if I create a new project. However, this same setup added to the existing demo project (with the ZYNQ7 Processing System) does not work. In this case, I have a Pmod ENC: Rotary Encoder connected to JB. In the new project, the LEDs indicate input from the encoder just fine, but on the existing demo project this does not work. My assumption is that something other than my constraint file data is controlling this information in the demo project. I'm not sure where/how to change that behavior. Thank you!

I am attempting to connect a Pmod to JA or JB of an Arty Z7-20. I tried manually updating the constraints file, and I don't seem to be getting data from the port. I then tried to use the Board tab in the block design to add JA. I get the error in the attached image if I try to add either of the Pmod ports. I am using Vivado 2022.1, and I believe I have the latest board files and constraint file. How can I resolve this? Thanks!

I was able to resolve this with the help of captain_wiggles_ over on r/FPGA. He/she pointed out that my frame pointer was a 32-bit pointer. I changed it to an 8-bit pointer and am writing the three bytes for red, green, and blue independently. Here is an updated function that prints a nice yellow box:

I am currently working on a small project that requires rendering text and shapes to the HDMI output. I am using an Arty Z7-20. While I have the basic content rendering fine, I am struggling to get the colors I would expect. I am trying to get white, but I am running into an issue where the output is not white but banded with different colors. Below, I would expect a clean white for all characters and all rectangles, but the color varies column by column. Also, I haven't been able to figure out how to get anything other than white, black, or grey; I end up with odd patterns. I expect I am either not writing the appropriate color data to the appropriate bytes, the wrong number of bytes, or something in the block design is misconfigured. I started with the HDMI Out Demo from Digilent and have added a couple of simple functions in Vitis to draw characters and rectangles. I have tried both an LCD and capturing the video on my PC -- both show similar issues. I posted a quick video to give a bit more context. Any suggestions would be appreciated. Coding issue, block diagram issue, limitation of the Z7 or of the demo project, other? Thanks!! Edit: Here's an output and the corresponding block of code that should fill a 100x100 region with red. I get red on the first vertical column, but then gaps moving to the right. If I use 0xFFFFFFFF for the color, I will get a solid white region.

Ok, no worries, @Arthur. I was able to re-use some code I had for drawing shapes and text in an Arty A7 project (VGA pmod). I have text and shape data working (mostly). However, as I'm trying to set colors for areas, the results do not match what I would expect to see. Can you point me in the direction of any resources that describe how to properly set color data for pixels using the HDMI Out project? In the Vivado block design, the AXI4-Stream to Video Out is using RGB for the video format. As I work with the frame in Vitis, I would expect that I set a 3-byte value for the color. I can get white, black, and grey, but when I try other colors, the results aren't what I would expect. For example, I get a rainbow effect when I would expect a solid color. I am likely missing something simple. Thanks! Edit: As this is a spin-off of the initial post, I started a new post with additional details.

I am just starting to work with an Arty Z7 and its HDMI output capabilities. I would like to generate text and basic graphics to overlay on the video output --within Vitis. Is there a library to support generation of text, versus pixel by pixel creation of text? Same question for basic graphics (shapes, fills, etc.). I am looking through this example which seems to have pixel by pixel code. I've worked with the OLEDrgb Pmod on my A7 before. It has text/shape support (PmodOLEDrgb.c). Possibly this library can be adapted (or already has been adapted)? Thanks!

I installed the Win10 14.7 package. All seemed to go well, and the software appears to be running fine. I ordered a C2 and S6, so I'll get to try these out. I did see them both listed in the device list in the app.

Thanks, @zygot. I see Xilinx packaged the old ISE 14.7 for Win10. I'll try to get that running on one of my old PCs. I never like the feeling of going back to old software. :)

I just stumbled across Learn.Digilentinc | Signal Propagation Delays. "...a circuit implemented in a modern FPGA will typically have delays that are much smaller than a circuit implemented in a five-year-old FPGA, and in turn, both FPGA circuits would have far smaller delays than a similar circuit built from discrete gates." A lot of good info in the article.

Can I program the C2 from the current Vivado toolset? In the C2 manual, it references the ISE WebPACK, but I was thinking Xilinx did away with the WebPACK, rolling it into Vivado. I have the Digilent boards added to my Vivado (2021.2.1), but I don't see any options for the C2 under Boards. Thank you!

Thanks for the info, @zygot and @asmi. I have updated the logic a bit. Below is the current logic and the LUT information from the implementation. I'm not only comparing apples to oranges, I'm probably comparing fruits to vegetables (or worse). :) As far as CPLDs, is the Cmod C2 the only CPLD from Digilent? I do think the CPLD would be a better solution, assuming it's timing for basics like this are comparable. I'll have to order one to compare. To give a little more context to what I'm trying to accomplish... I am building a 65816-based system, and for the prototyping phase, I'm looking to use an FPGA/CPLD for the address decode logic -- rather than use discrete ICs. This will provide me more flexibility in changing the decode logic without rewiring ICs. Once I finalize the logic design, I'll implement the solution with discrete ICs (e.g., the fastest 74 series of gates I can order). While the 65816 processor I am using supports 14 MHz, I expect the surrounding logic ICs will be the limiting factor to the clock speed I can run. I'm able to add up the propagation delays of the ICs, based on the data sheets. I'm trying to get a good feel for how the FPGA/CPLD will compare in timing performance. Of course, once I get things connected and running, I can check out the timings on the scope.

For a simple circuit such as that in the image below, will I see a difference in propagation delays (at each gate) when implemented on the three different Cmods (S6, A7-15T, A7-35T)? I am working to understand general timings of these Cmods. I have an A7-35T and will implement the circuit and review timings. I'm curious if a less expensive S6 will have similar timings or if it will be slower. Related, I'm looking to understand how these timings compare to discrete ICs in the 74AC series. Will an FPGA be faster or slower than the comparable logic ICs (74AC series)? Thanks! Edit: I implemented the following design on the Cmod S7, A7-15T, and A7-35T. I did not test the S6, as it's not supported in Vivado. From what I am seeing, it seems like the two A7 Cmods have identical delays, and the S7 is a bit slower. I would assume then that the S6 would be slower than the S7. As I look at Total Delay, the values seem lower than the total delay would be with discrete ICs. Based on this, my interpretation is that this logic in these Cmods would be faster than an equivalent circuit with discrete ICs. Does that sound right?

I'll dig into it. Thanks, @JColvin!

@JColvin, those LVLSHFT Pmods worked great. If you're interested: https://www.rehsdonline.com/post/fpga-vga-for-6502-first-run. Thanks!

I'm looking for wisdom and guidance... ? I'm trying to get VGA output from a Cmod A7. I'm curious if this should be possible, or if it's a bad path to pursue. I've captured information on my progress with it here: https://www.rehsdonline.com/post/attempting-vga-from-cmod-a7. Any suggestions would be appreciated. Thank you! Update: I was able to resolve the issue (rows on the Pmod connector cables were reversed). I updated the link above with more details and sample video output.

To further clarify, I would use this config for the Pmod LVLSHFT:

I am looking to bring 16 digital signals that are 5v into a Cmod A7 (and/or Arty A7, possibly) and then output a VGA signal. I plan to use the Cmod A7, a pair of LVLSHFT Pmods, and a VGA Pmod. The communication is one-way, from the VIA to the Cmod. Before I actually hook this up and manage to damage my Cmod, does this seem like a reasonable approach? Any gotchas here? Thanks!

That's very helpful, @JColvin. Thank you!

Where can I find documentation for the Digilent Dynamic Clock Generator IP core? The link from the Vivado Library page is broken. It links to: https://github.com/Digilent/vivado-library/tree/master/ip/axi_dynclk_v1_1 I'm not seeing any sort of documentation in axi_dynclk, but I could be missing it. Thanks.

In case anyone is interested, I posted a walkthrough of setting up an Arty A7-100T with the VGA Pmod, controlled by MicroBlaze. Suggestions to improve the write-up are welcome. Thanks! https://www.rehsdonline.com/post/arty-vga-walkthrough

The information provided for the Shield does not seem to explain it very well. For example, how can I leverage the Shield JE connector from my Arty? I cannot find a sample XDC file that includes JE, and I'm questioning whether JA on the Arty XDC is the same as JA on the Shield. Regarding JA-JE, the Shield Reference Manual states, "These connectors provide access to the signals of the host in a form factor which readily allows Digilent Pmods to be connected. UART, SPI and GPIO protocols are supported via the Pmod connectors." I have looked at the Shield schematic, but I'm not following how the schematic ties back to the Arty. Or is the shield only supplying JA-JE to an onboard Arduino, and really doesn't have anything to do with the Arty onboard JA-JD connectors? Product Update Annoucement – Digilent Pmod Shield Rev B Pmod Shield Are there any example XDC files, project files, etc. to help understand the Shield better (and how it's intended to be used)? Thank you.