ignored `define statement in Technical Based Off-Topic Discussions Posted November 4, 2021 · Edited November 4, 2021 by dcwestcott more detail I have the following that does not work in Xilinx Vivado Simulator 2019: `ifdef FPGA 'define MAX_MEMORY 1024 `else // ASIC `define MAX_MEMORY 2048 `endif I've seen posts that say you can not do this, but Is there a structure I can use that will do this function without manually controlling parameters?
ignored `define statement
in Technical Based Off-Topic Discussions
Posted · Edited by dcwestcott
more detail
I have the following that does not work in Xilinx Vivado Simulator 2019:
`ifdef FPGA
'define MAX_MEMORY 1024
`else // ASIC
`define MAX_MEMORY 2048
`endif
I've seen posts that say you can not do this, but Is there a structure I can use that will do this function without manually controlling parameters?