Hi @mirabelle275,
I haven't used Matlab or Simulink in combination with Xilinx's tools, so I'm not certain what you would need to do on that end of things.
As for the create_clock constraint, it does not actually create a clock. It just tells the Vivado software that this particular net should be treated as a clock while it goes through its various synthesis and optimization steps. Pin E3 itself on the Nexys A7 is connected to a 100 MHz oscillator on the board, so you cannot actually change this frequency. You would need to use a clock management tile to be able to create a different clock frequency from the 100 MHz line, though I don't know this would be done in MATLAB; this might be a good resource for you, https://www.mathworks.com/help/hdlcoder/ug/using-multiple-clocks-in-hdl-coder.html, though otherwise you'll probably need to ask on MATLAB Answers, https://www.mathworks.com/matlabcentral/answers/index/?s_tid=gn_mlc_an, to get more specific help.
Thanks,
JColvin
