HomaGOD
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Posts posted by HomaGOD
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Excuse me, can any professional help me check the question?
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On 11/8/2021 at 3:43 PM, thinkthinkthink said:
This is the error I was getting, but look at what it says when I scroll to the right. BRAM has overflowed.
I just remember that your error about BRAM might should be related to the following settings. In my design, I set Local Memory optons as 32KB.
This might explain why I do not met with an error as yours.
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7 hours ago, thinkthinkthink said:
Well you need to add an axi uartlite to your block design cuz the uart inside PmodBT2 is for a different purpose.
Could you please give a more detailed description of the uart inside PmodBT2?
Then, I add an axi uartlite to my block design, re-generate bitstream and build the platform and application project.
But no error occurs, especially related to BRAM, which is shocking.
The next two screen-captures are console info after I build the application.
Still, sometimes after I build application project, it prompts that make: Nothing to be done for 'all'.
What is the difference between the two parts that the arrow points to in the next screen-capture?
Thanks a lot in advance.
Wish your reply.
HomaGOD.
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4 hours ago, thinkthinkthink said:
Do you even have an AXI UartLite IP in your block design ? If not you have to add it, re-Generate Bitstream and export hardware, then go to Vitis, right click on your hardware platform and select Update Hardware Specification.
I do not add an AXI UartLite IP in my block design in that I remember a digilent engineer told me that there is already an UART ip in PmodBT2.
According to your hint, I right click on my hardware platform and select Update Hardware Specification, but it failed. The error info is as follows.
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1 hour ago, thinkthinkthink said:
Only 8 pins are connected to the FPGA, pins 6 and 12 are VCC_3V3 while pins 5 and 11 are GND.
I see. Thank you for your reply.
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23 hours ago, thinkthinkthink said:
This is the error I was getting, but look at what it says when I scroll to the right. BRAM has overflowed.
To change stdin and stdout you can just choose from the dropdown list in their Value field.
Thanks for your warm reply!
Strange is that I can not set the value of stdin and stdout as axi_uartlite_0. The dropdown list of of Value field is none like this. I do not know what went wrong.
Secondly, the error you presented really makes sense. But, strange is that the results of my building platform and application are quite different from yours.
Everytime when I build application, it always prompts fatal error: xuartlite.h: No such file or directory, which confuses me a lot.
I attach the .xsa file, would you please spare time to check what went wrong if convenient?
Thanks a lot.
HomaGOD.
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Hello, all professionals
There are 12 pins of every Pmod interface, but I discover only 10 of 12 pins are constrained to FPGA(as is described in the following screen-capture). Does that mean that the remaining two pins are not connected to FPGA?
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On 11/4/2021 at 4:56 PM, thinkthinkthink said:
Go to your hardware platform in vitis and double click on platform.spr, once that opens click on the Modify BSP Settings... button.
A new window will popup and then go to standalone under the Overview dropdown. Make sure that both stdin and stdout have their Value field set to axi_uartlite_0 (or whatever name your axi uartlite ip that you added later has). If you had to change them then don't forget to rebuild the whole workspace (meaning both the hardware platform and the application project).
I don't get any of the errors you get while trying to create a project like yours, except that Vitis can't create an .elf file and my theory, just like James Colvin has told you, is that unfortunately the Basys3 does not have sufficient BRAM and no RAM to run applications like this one.
Many thanks to your warm reply and sorry for my late reply.
First, Confusing is that when I clicks on the Modify BSP Settings... button, the value of both stdin and stdout is NONE ratherthan axi_uartlite_0. Would you please be so kind to give me some guidance.
Second, I noticed that there is an error in your screen capture of kojima_system tab as is marked in the following figrue. Could you be please provide a figure with that error if convenient? Thank you.
Besides, I have confusion about the theory you and James Colvin have told me.
I have looked up to the user manual of Basys3, which says it has 50 BRAM, with every BRAM's scale is 36kb, thus Basys3 can provide 225KB(50*36kb/8) size of BRAM. Meantime, I open the implemented design and report the utilization of the whole board design. It prompts that it only consuming 8% of the BRAM.
Therefore, I do not know how to judge whether Basys3 has sufficient BRAM to run applications like BlueTooth transmission. In other words, what is the common basis of judgment?
Finally, what I want to add is that this link http://digilent.com.cn/community/222.html#top gives a proof that Basys3 can run demo application (print some info).
But the above design's demo program is unlike main.c in directory xxx\drivers\PmodBT2_v1_0\examples, maybe different versions of example program require different BRAM? Of course, this is only my personal guess.
Wish your reply, when convenient.
Thanks,
HomaGOD
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17 hours ago, Ana-Maria Balas said:
Could you post a screencapture of your whole block design from Vivado? Then screen capture from the Adress Editor tab?
Thanks for your reply and sorry for the late reply.
Next is the whole block design from Vivado.
This figure is screen capture from the Address Editor tab and .hdf file read in SDK.
For convenience, I want to upload the whole project file created in vivado2017.4. That is because that the tool can't find the Microblaze GCC like the following screen capture. But there is a limit of file size, is there any other alternative?
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Quote
To clarify, the Pmod AMP2 is only an amplifier; it does not take inputs from the audio jack to go back to the system board.
In my understanding, AMP2 does not have ADC, thus cannot take inputs from the audio jack, then go back to the system board.
Besides, the amplified signal should be digital signal. Is that right?
Thanks,
HomaGOD
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6 hours ago, thinkthinkthink said:
The PmodBT2 IP already contains an UART IP inside it no need to add another one in your block design, you just need to look in the xparameters.h header file for the correct DEVICE ID of that UART.
Strange is that I do not find the DEVICE ID in the xparameters.h, which confuses me a lot.
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3 hours ago, thinkthinkthink said:
Have you looked in xparameters.h for the correct definition of your uart's DEVICE ID ?
I looked up to it. The error finally is resolved when I add axi_uartlite IP to board design diagram.
However, when I run the applicaiton project as "Launch on Hardware", Recv data displays all zero in HEX and space in ASCII on UartAssist as follows.
The correct situation should be that Recv HEX displays "Initialized PmodBT2 Demo Received data will be echoed here, type to send data". It seems that FPGA cannot send data to PC. How should I find where the problems exist?
Thank you very much.
HomaGOD
The next screenshot display the running info when I run as Hardware, which I think might help you judge the porblem.
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This is the initial error when I re-install vivado2015.3 and re-build microblaze.
Still, same error occur, which makes me collapsed.
Having tried numerous ways, they ALL turn to fail.
Wish your help, all engineers and professionals.
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When building microblaze in SDK, it prompts that some parameters are undefined, especially those related to axi_uartlite.(Does that be related to not adding )
For example, #define SYS_UART_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID can not be found during executing.
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On the one hand, I use 2018.3 version of Vivado and VivadoSDK 2018.3 to build microblaze. But it prompts mb-gcc tool can not be found as the following screenshot.
On the other hand, I re-install antother newer version of Vivado2020.1 and use included new tool Vitis to build microblaze to verify the function of PmodBT2. Unfortunately, still many errors occur. The error says that "Unresolved inclusion: "xuartlite.h" " But when I add the .h file to the directory, another error occurs 'XPAR_AXI_UARTLITE_0_DEVICE_ID' undeclared (first use in this function)
Finally, I wonder if I have to add AXI Uartlite IP in board design. Next is my board design diagram, would you please help me if there exists some problems?
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As is described before, I have been developing PmodBT2 using microblaze. After I generate bit file, I lanuch SDK, many errors occur as follows.
And vivado version is 2018.3. Is there anyone to give me some guidance? I spent several hours, but still fail.
Wish your reply. Thanks a lot.
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16 hours ago, JColvin said:
Hi @HomaGOD,
I'm not really able to comment if this Pmod will work with the Basys 3. Yes, it is physically compatible with the Basys 3 and the verilog code on their GitHub, https://github.com/scanlime/icebreaker-video-stuff, will be able to run on the Basys 3 (you'll need to adjust the pin constraints of course), but I don't know how the hardware capabilities of the iCEBreaker FPGA compare with the Basys 3. It seems like the iCEBreaker FPGA has 33 ohm series resistors on their Pmod lines whereas the Basys 3 has 200 ohm resistors on it's Pmod ports so you would lose some speed there, but maybe it would still work. I haven't done the research comparing the FPGA IO switching characteristics nor have the hardware to test this.
Thanks,
JColvinThanks for your detailed reply, which solves my numerous questions.
I have another problem. Is there any reference resources of PmodAMP2 related to PWM-style audio signal processing?
Wish your reply.
Thanks,
HomaGOD
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9 hours ago, JColvin said:
Hi @HomaGOD,
So, the application is the software material (usually written in C) that comes with the Pmod IPs to have them work with the processor on the board (usually Microblaze for non-Zynq based boards or the existing ARM processor on the Zynq boards). Each of these applications (and processor to run them in the case of Microblaze) take some amount of memory to successfully run.
The Basys 3, unlike most of our other boards, does not have any extra external memory to help hold and run these applications; it only has the limited amount of block RAM that comes with the Artix 7 35T FPGA that is present on the Basys 3, which is insufficient to be able to hold the WiFi stack (Pmod WiFi) or the SD card library (Pmod SD/Pmod microSD).
As for knowing if the Basys 3 has enough memory to run the Pmod BT2, the only real way to know is to make the product in your desired version of Vivado, generate the bitstream, export the project, then build it in SDK/Vitis (depending on what version of the Xilinx software you choose) and see if you get a memory error. I can't really say for certain offhand if the Basys 3 has enough memory or not since it depends on what version of Vivado you are using as well as what IPs and materials you incorporate into the block design.
Let me know if you have any questions.
Thanks,
JColvinI see, Thanks for your detailed explanation.
And plus, I have another problem in the link
Would you please be kind to spare time to answer it? Thanks a lot.
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5 hours ago, D@n said:
HDMI tends to require more pins than a typical PMod can support. That said, have you looked at this PMod? It's not Digilent, but it does look like it might have some promise.
Dan
The following device(the upper figure) requires two 12 pins of Pmod, which Basys3 supports.
The exact link relation can be like the lower figure. I don't know where I understand it wrong.
Thanks for your reply, wish your answers.
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I know Basys3 board has VGA type interface to display figure.
Now I want to know if there is a Pmod that supports HDMI-type?
Wish your reply, thanks.
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Via this link https://digilent.com/blog/digilent-pmods-audio-pmods/, I conclude that PmodAMP2 supports PWM input audio signal.
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And PmodAMP3 does not support PWM input?
I wonder if I have true understanding about these two audio-related Pmod.
Wish your reply.
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15 hours ago, JColvin said:
Hi @HomaGOD,
The Basys 3 might be able to communicate with the Pmod BT2 via the Pmod BT2 IP core, though I don't know if the Basys 3 has enough memory for the application; we have a guide on how to use Pmod IP cores for Vivado and SDK (2019.1 and earlier) here, and a newer one that walks through setting up a design in Vivado and Vitis (2019.2 and later) here.
The Pmod WiFi will not work on the Basys 3 though because it does not have enough memory (and no external memory) to be able to hold the needed software to run the WiFi application.
Let me know if you have any questions.
Thanks,
JColvinThanks for your timely reply.
You referred that you are nor sure whether Basys3 has enough memory for the application. I am confused what "application" refers to here.
And plus, how should I judge if Basys3 has enough memory to link to the Pmod BT2?
Hope your reply.
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For example, is there any chance that BASYS3 can communicate with PmodWiFi and PmodBT2?
If yes, how should it be realized? I am confused about it.
Hope your reply, thanks a lot.
The direction of Col signals in PmodKYPD are output.
in Add-on Boards
Posted
As for the point, I feel confused. In my understanding, Row signals and Col signals decides the excat pressed button together, thus they should all be input signals.
I wonder if there is any professional is kind to help me reply to confusion.
Thanks a lot.